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@@ -769,6 +769,14 @@ static int r600_parse_clk_voltage_dep_table(struct radeon_clock_voltage_dependen
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return 0;
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}
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+/* sizeof(ATOM_PPLIB_EXTENDEDHEADER) */
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+#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V2 12
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+#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V3 14
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+#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V4 16
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+#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5 18
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+#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V6 20
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+#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V7 22
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+
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int r600_parse_extended_power_table(struct radeon_device *rdev)
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{
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struct radeon_mode_info *mode_info = &rdev->mode_info;
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@@ -925,6 +933,43 @@ int r600_parse_extended_power_table(struct radeon_device *rdev)
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}
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}
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+ /* ppm table */
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+ if (le16_to_cpu(power_info->pplib.usTableSize) >=
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+ sizeof(struct _ATOM_PPLIB_POWERPLAYTABLE3)) {
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+ ATOM_PPLIB_EXTENDEDHEADER *ext_hdr = (ATOM_PPLIB_EXTENDEDHEADER *)
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+ (mode_info->atom_context->bios + data_offset +
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+ le16_to_cpu(power_info->pplib3.usExtendendedHeaderOffset));
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+ if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5) &&
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+ ext_hdr->usPPMTableOffset) {
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+ ATOM_PPLIB_PPM_Table *ppm = (ATOM_PPLIB_PPM_Table *)
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+ (mode_info->atom_context->bios + data_offset +
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+ le16_to_cpu(ext_hdr->usPPMTableOffset));
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+ rdev->pm.dpm.dyn_state.ppm_table =
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+ kzalloc(sizeof(struct radeon_ppm_table), GFP_KERNEL);
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+ if (!rdev->pm.dpm.dyn_state.ppm_table)
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+ return -ENOMEM;
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+ rdev->pm.dpm.dyn_state.ppm_table->ppm_design = ppm->ucPpmDesign;
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+ rdev->pm.dpm.dyn_state.ppm_table->cpu_core_number =
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+ le16_to_cpu(ppm->usCpuCoreNumber);
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+ rdev->pm.dpm.dyn_state.ppm_table->platform_tdp =
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+ le32_to_cpu(ppm->ulPlatformTDP);
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+ rdev->pm.dpm.dyn_state.ppm_table->small_ac_platform_tdp =
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+ le32_to_cpu(ppm->ulSmallACPlatformTDP);
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+ rdev->pm.dpm.dyn_state.ppm_table->platform_tdc =
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+ le32_to_cpu(ppm->ulPlatformTDC);
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+ rdev->pm.dpm.dyn_state.ppm_table->small_ac_platform_tdc =
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+ le32_to_cpu(ppm->ulSmallACPlatformTDC);
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+ rdev->pm.dpm.dyn_state.ppm_table->apu_tdp =
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+ le32_to_cpu(ppm->ulApuTDP);
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+ rdev->pm.dpm.dyn_state.ppm_table->dgpu_tdp =
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+ le32_to_cpu(ppm->ulDGpuTDP);
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+ rdev->pm.dpm.dyn_state.ppm_table->dgpu_ulv_power =
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+ le32_to_cpu(ppm->ulDGpuUlvPower);
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+ rdev->pm.dpm.dyn_state.ppm_table->tj_max =
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+ le32_to_cpu(ppm->ulTjmax);
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+ }
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+ }
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+
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return 0;
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}
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@@ -940,4 +985,6 @@ void r600_free_extended_power_table(struct radeon_device *rdev)
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kfree(rdev->pm.dpm.dyn_state.cac_leakage_table.entries);
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if (rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries)
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kfree(rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries);
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+ if (rdev->pm.dpm.dyn_state.ppm_table)
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+ kfree(rdev->pm.dpm.dyn_state.ppm_table);
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}
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