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@@ -2001,18 +2001,29 @@ void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
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/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
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* is assumed to be a power-of-two. */
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-unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
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- unsigned int bpp,
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- unsigned int pitch)
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+unsigned long intel_gen4_compute_page_offset(int *x, int *y,
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+ unsigned int tiling_mode,
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+ unsigned int cpp,
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+ unsigned int pitch)
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{
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- int tile_rows, tiles;
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+ if (tiling_mode != I915_TILING_NONE) {
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+ unsigned int tile_rows, tiles;
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- tile_rows = *y / 8;
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- *y %= 8;
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- tiles = *x / (512/bpp);
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- *x %= 512/bpp;
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+ tile_rows = *y / 8;
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+ *y %= 8;
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- return tile_rows * pitch * 8 + tiles * 4096;
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+ tiles = *x / (512/cpp);
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+ *x %= 512/cpp;
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+
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+ return tile_rows * pitch * 8 + tiles * 4096;
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+ } else {
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+ unsigned int offset;
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+
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+ offset = *y * pitch + *x * cpp;
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+ *y = 0;
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+ *x = (offset & 4095) / cpp;
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+ return offset & -4096;
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+ }
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}
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static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
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@@ -2089,9 +2100,9 @@ static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
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if (INTEL_INFO(dev)->gen >= 4) {
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intel_crtc->dspaddr_offset =
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- intel_gen4_compute_offset_xtiled(&x, &y,
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- fb->bits_per_pixel / 8,
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- fb->pitches[0]);
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+ intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
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+ fb->bits_per_pixel / 8,
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+ fb->pitches[0]);
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linear_offset -= intel_crtc->dspaddr_offset;
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} else {
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intel_crtc->dspaddr_offset = linear_offset;
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@@ -2182,9 +2193,9 @@ static int ironlake_update_plane(struct drm_crtc *crtc,
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linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
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intel_crtc->dspaddr_offset =
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- intel_gen4_compute_offset_xtiled(&x, &y,
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- fb->bits_per_pixel / 8,
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- fb->pitches[0]);
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+ intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
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+ fb->bits_per_pixel / 8,
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+ fb->pitches[0]);
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linear_offset -= intel_crtc->dspaddr_offset;
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DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
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