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@@ -1290,6 +1290,11 @@ static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_Q
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MLX5_QP_OPTPAR_Q_KEY,
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[MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX |
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MLX5_QP_OPTPAR_Q_KEY,
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+ [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
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+ MLX5_QP_OPTPAR_RRE |
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+ MLX5_QP_OPTPAR_RAE |
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+ MLX5_QP_OPTPAR_RWE |
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+ MLX5_QP_OPTPAR_PKEY_INDEX,
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},
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},
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[MLX5_QP_STATE_RTR] = {
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@@ -1325,6 +1330,10 @@ static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_Q
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[MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
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[MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
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[MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE,
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+ [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT |
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+ MLX5_QP_OPTPAR_RWE |
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+ MLX5_QP_OPTPAR_RAE |
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+ MLX5_QP_OPTPAR_RRE,
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},
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},
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};
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