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@@ -1,7 +1,7 @@
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/*******************************************************************************
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Intel 10 Gigabit PCI Express Linux driver
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- Copyright(c) 1999 - 2010 Intel Corporation.
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+ Copyright(c) 1999 - 2011 Intel Corporation.
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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@@ -46,10 +46,7 @@ static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
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static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
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static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
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-static void ixgbe_enable_rar(struct ixgbe_hw *hw, u32 index);
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-static void ixgbe_disable_rar(struct ixgbe_hw *hw, u32 index);
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static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
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-static void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq);
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static s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num);
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/**
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@@ -454,8 +451,7 @@ s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
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* Prevent the PCI-E bus from from hanging by disabling PCI-E master
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* access and verify no pending requests
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*/
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- if (ixgbe_disable_pcie_master(hw) != 0)
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- hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
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+ ixgbe_disable_pcie_master(hw);
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return 0;
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}
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@@ -603,7 +599,6 @@ s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
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ixgbe_shift_out_eeprom_bits(hw, data, 16);
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ixgbe_standby_eeprom(hw);
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- msleep(hw->eeprom.semaphore_delay);
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/* Done with writing - release the EEPROM */
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ixgbe_release_eeprom(hw);
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}
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@@ -747,10 +742,10 @@ s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
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static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
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{
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s32 status = 0;
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- u32 eec = 0;
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+ u32 eec;
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u32 i;
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- if (ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0)
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+ if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0)
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status = IXGBE_ERR_SWFW_SYNC;
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if (status == 0) {
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@@ -773,18 +768,18 @@ static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
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IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
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hw_dbg(hw, "Could not acquire EEPROM grant\n");
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- ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
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+ hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
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status = IXGBE_ERR_EEPROM;
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}
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- }
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- /* Setup EEPROM for Read/Write */
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- if (status == 0) {
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- /* Clear CS and SK */
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- eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
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- IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
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- IXGBE_WRITE_FLUSH(hw);
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- udelay(1);
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+ /* Setup EEPROM for Read/Write */
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+ if (status == 0) {
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+ /* Clear CS and SK */
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+ eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
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+ IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
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+ IXGBE_WRITE_FLUSH(hw);
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+ udelay(1);
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+ }
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}
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return status;
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}
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@@ -798,13 +793,10 @@ static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
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static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
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{
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s32 status = IXGBE_ERR_EEPROM;
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- u32 timeout;
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+ u32 timeout = 2000;
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u32 i;
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u32 swsm;
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- /* Set timeout value based on size of EEPROM */
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- timeout = hw->eeprom.word_size + 1;
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-
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/* Get SMBI software semaphore between device drivers first */
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for (i = 0; i < timeout; i++) {
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/*
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@@ -816,7 +808,7 @@ static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
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status = 0;
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break;
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}
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- msleep(1);
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+ udelay(50);
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}
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/* Now get the semaphore between SW/FW through the SWESMBI bit */
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@@ -844,11 +836,14 @@ static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
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* was not granted because we don't have access to the EEPROM
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*/
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if (i >= timeout) {
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- hw_dbg(hw, "Driver can't access the Eeprom - Semaphore "
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+ hw_dbg(hw, "SWESMBI Software EEPROM semaphore "
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"not granted.\n");
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ixgbe_release_eeprom_semaphore(hw);
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status = IXGBE_ERR_EEPROM;
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}
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+ } else {
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+ hw_dbg(hw, "Software semaphore SMBI between device drivers "
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+ "not granted.\n");
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}
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return status;
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@@ -1081,10 +1076,13 @@ static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
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IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
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ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
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+
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+ /* Delay before attempt to obtain semaphore again to allow FW access */
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+ msleep(hw->eeprom.semaphore_delay);
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}
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/**
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- * ixgbe_calc_eeprom_checksum - Calculates and returns the checksum
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+ * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
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* @hw: pointer to hardware structure
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**/
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u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
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@@ -1190,7 +1188,7 @@ s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
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if (status == 0) {
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checksum = hw->eeprom.ops.calc_checksum(hw);
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status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM,
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- checksum);
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+ checksum);
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} else {
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hw_dbg(hw, "EEPROM read failed\n");
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}
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@@ -1238,37 +1236,37 @@ s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
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u32 rar_low, rar_high;
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u32 rar_entries = hw->mac.num_rar_entries;
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+ /* Make sure we are using a valid rar index range */
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+ if (index >= rar_entries) {
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+ hw_dbg(hw, "RAR index %d is out of range.\n", index);
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+ return IXGBE_ERR_INVALID_ARGUMENT;
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+ }
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+
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/* setup VMDq pool selection before this RAR gets enabled */
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hw->mac.ops.set_vmdq(hw, index, vmdq);
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- /* Make sure we are using a valid rar index range */
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- if (index < rar_entries) {
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- /*
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- * HW expects these in little endian so we reverse the byte
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- * order from network order (big endian) to little endian
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- */
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- rar_low = ((u32)addr[0] |
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- ((u32)addr[1] << 8) |
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- ((u32)addr[2] << 16) |
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- ((u32)addr[3] << 24));
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- /*
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- * Some parts put the VMDq setting in the extra RAH bits,
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- * so save everything except the lower 16 bits that hold part
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- * of the address and the address valid bit.
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- */
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- rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
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- rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
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- rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
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+ /*
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+ * HW expects these in little endian so we reverse the byte
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+ * order from network order (big endian) to little endian
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+ */
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+ rar_low = ((u32)addr[0] |
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+ ((u32)addr[1] << 8) |
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+ ((u32)addr[2] << 16) |
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+ ((u32)addr[3] << 24));
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+ /*
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+ * Some parts put the VMDq setting in the extra RAH bits,
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+ * so save everything except the lower 16 bits that hold part
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+ * of the address and the address valid bit.
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+ */
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+ rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
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+ rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
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+ rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
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- if (enable_addr != 0)
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- rar_high |= IXGBE_RAH_AV;
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+ if (enable_addr != 0)
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+ rar_high |= IXGBE_RAH_AV;
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- IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
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- IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
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- } else {
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- hw_dbg(hw, "RAR index %d is out of range.\n", index);
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- return IXGBE_ERR_RAR_INDEX;
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- }
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+ IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
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+ IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
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return 0;
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}
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@@ -1286,58 +1284,26 @@ s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
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u32 rar_entries = hw->mac.num_rar_entries;
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/* Make sure we are using a valid rar index range */
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- if (index < rar_entries) {
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- /*
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- * Some parts put the VMDq setting in the extra RAH bits,
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- * so save everything except the lower 16 bits that hold part
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- * of the address and the address valid bit.
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- */
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- rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
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- rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
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-
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- IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
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- IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
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- } else {
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+ if (index >= rar_entries) {
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hw_dbg(hw, "RAR index %d is out of range.\n", index);
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- return IXGBE_ERR_RAR_INDEX;
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+ return IXGBE_ERR_INVALID_ARGUMENT;
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}
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- /* clear VMDq pool/queue selection for this RAR */
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- hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
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-
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- return 0;
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-}
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-
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-/**
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- * ixgbe_enable_rar - Enable Rx address register
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- * @hw: pointer to hardware structure
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- * @index: index into the RAR table
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- *
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- * Enables the select receive address register.
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- **/
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-static void ixgbe_enable_rar(struct ixgbe_hw *hw, u32 index)
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-{
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- u32 rar_high;
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-
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+ /*
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+ * Some parts put the VMDq setting in the extra RAH bits,
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+ * so save everything except the lower 16 bits that hold part
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+ * of the address and the address valid bit.
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+ */
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rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
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- rar_high |= IXGBE_RAH_AV;
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+ rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
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+
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+ IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
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IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
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-}
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-/**
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- * ixgbe_disable_rar - Disable Rx address register
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- * @hw: pointer to hardware structure
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- * @index: index into the RAR table
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- *
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- * Disables the select receive address register.
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- **/
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-static void ixgbe_disable_rar(struct ixgbe_hw *hw, u32 index)
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-{
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- u32 rar_high;
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+ /* clear VMDq pool/queue selection for this RAR */
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+ hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
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- rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
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- rar_high &= (~IXGBE_RAH_AV);
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- IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
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+ return 0;
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}
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/**
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@@ -1386,7 +1352,6 @@ s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
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}
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/* Clear the MTA */
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- hw->addr_ctrl.mc_addr_in_rar_count = 0;
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hw->addr_ctrl.mta_in_use = 0;
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IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
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@@ -1400,105 +1365,6 @@ s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
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return 0;
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}
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-/**
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- * ixgbe_add_uc_addr - Adds a secondary unicast address.
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- * @hw: pointer to hardware structure
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- * @addr: new address
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- *
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- * Adds it to unused receive address register or goes into promiscuous mode.
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- **/
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-static void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
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-{
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- u32 rar_entries = hw->mac.num_rar_entries;
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- u32 rar;
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-
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- hw_dbg(hw, " UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
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- addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
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-
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- /*
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- * Place this address in the RAR if there is room,
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- * else put the controller into promiscuous mode
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- */
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- if (hw->addr_ctrl.rar_used_count < rar_entries) {
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- rar = hw->addr_ctrl.rar_used_count -
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- hw->addr_ctrl.mc_addr_in_rar_count;
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- hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
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- hw_dbg(hw, "Added a secondary address to RAR[%d]\n", rar);
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- hw->addr_ctrl.rar_used_count++;
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- } else {
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- hw->addr_ctrl.overflow_promisc++;
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- }
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-
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- hw_dbg(hw, "ixgbe_add_uc_addr Complete\n");
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-}
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-
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-/**
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- * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
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- * @hw: pointer to hardware structure
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- * @netdev: pointer to net device structure
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- *
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- * The given list replaces any existing list. Clears the secondary addrs from
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- * receive address registers. Uses unused receive address registers for the
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- * first secondary addresses, and falls back to promiscuous mode as needed.
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- *
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- * Drivers using secondary unicast addresses must set user_set_promisc when
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- * manually putting the device into promiscuous mode.
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- **/
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-s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw,
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- struct net_device *netdev)
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-{
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- u32 i;
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- u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
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- u32 uc_addr_in_use;
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- u32 fctrl;
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- struct netdev_hw_addr *ha;
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-
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- /*
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- * Clear accounting of old secondary address list,
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- * don't count RAR[0]
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- */
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- uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1;
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- hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
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- hw->addr_ctrl.overflow_promisc = 0;
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-
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- /* Zero out the other receive addresses */
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- hw_dbg(hw, "Clearing RAR[1-%d]\n", uc_addr_in_use + 1);
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- for (i = 0; i < uc_addr_in_use; i++) {
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- IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0);
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- IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0);
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- }
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-
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- /* Add the new addresses */
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- netdev_for_each_uc_addr(ha, netdev) {
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- hw_dbg(hw, " Adding the secondary addresses:\n");
|
|
|
- ixgbe_add_uc_addr(hw, ha->addr, 0);
|
|
|
- }
|
|
|
-
|
|
|
- if (hw->addr_ctrl.overflow_promisc) {
|
|
|
- /* enable promisc if not already in overflow or set by user */
|
|
|
- if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
|
|
|
- hw_dbg(hw, " Entering address overflow promisc mode\n");
|
|
|
- fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
|
|
|
- fctrl |= IXGBE_FCTRL_UPE;
|
|
|
- IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
|
|
|
- hw->addr_ctrl.uc_set_promisc = true;
|
|
|
- }
|
|
|
- } else {
|
|
|
- /* only disable if set by overflow, not by user */
|
|
|
- if ((old_promisc_setting && hw->addr_ctrl.uc_set_promisc) &&
|
|
|
- !(hw->addr_ctrl.user_set_promisc)) {
|
|
|
- hw_dbg(hw, " Leaving address overflow promisc mode\n");
|
|
|
- fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
|
|
|
- fctrl &= ~IXGBE_FCTRL_UPE;
|
|
|
- IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
|
|
|
- hw->addr_ctrl.uc_set_promisc = false;
|
|
|
- }
|
|
|
- }
|
|
|
-
|
|
|
- hw_dbg(hw, "ixgbe_update_uc_addr_list_generic Complete\n");
|
|
|
- return 0;
|
|
|
-}
|
|
|
-
|
|
|
/**
|
|
|
* ixgbe_mta_vector - Determines bit-vector in multicast table to set
|
|
|
* @hw: pointer to hardware structure
|
|
|
@@ -1550,7 +1416,6 @@ static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
|
|
|
u32 vector;
|
|
|
u32 vector_bit;
|
|
|
u32 vector_reg;
|
|
|
- u32 mta_reg;
|
|
|
|
|
|
hw->addr_ctrl.mta_in_use++;
|
|
|
|
|
|
@@ -1568,9 +1433,7 @@ static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
|
|
|
*/
|
|
|
vector_reg = (vector >> 5) & 0x7F;
|
|
|
vector_bit = vector & 0x1F;
|
|
|
- mta_reg = IXGBE_READ_REG(hw, IXGBE_MTA(vector_reg));
|
|
|
- mta_reg |= (1 << vector_bit);
|
|
|
- IXGBE_WRITE_REG(hw, IXGBE_MTA(vector_reg), mta_reg);
|
|
|
+ hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
|
|
|
}
|
|
|
|
|
|
/**
|
|
|
@@ -1596,18 +1459,21 @@ s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw,
|
|
|
hw->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev);
|
|
|
hw->addr_ctrl.mta_in_use = 0;
|
|
|
|
|
|
- /* Clear the MTA */
|
|
|
+ /* Clear mta_shadow */
|
|
|
hw_dbg(hw, " Clearing MTA\n");
|
|
|
- for (i = 0; i < hw->mac.mcft_size; i++)
|
|
|
- IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
|
|
|
+ memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
|
|
|
|
|
|
- /* Add the new addresses */
|
|
|
+ /* Update mta shadow */
|
|
|
netdev_for_each_mc_addr(ha, netdev) {
|
|
|
hw_dbg(hw, " Adding the multicast addresses:\n");
|
|
|
ixgbe_set_mta(hw, ha->addr);
|
|
|
}
|
|
|
|
|
|
/* Enable mta */
|
|
|
+ for (i = 0; i < hw->mac.mcft_size; i++)
|
|
|
+ IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
|
|
|
+ hw->mac.mta_shadow[i]);
|
|
|
+
|
|
|
if (hw->addr_ctrl.mta_in_use > 0)
|
|
|
IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
|
|
|
IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
|
|
|
@@ -1624,15 +1490,8 @@ s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw,
|
|
|
**/
|
|
|
s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
|
|
|
{
|
|
|
- u32 i;
|
|
|
- u32 rar_entries = hw->mac.num_rar_entries;
|
|
|
struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
|
|
|
|
|
|
- if (a->mc_addr_in_rar_count > 0)
|
|
|
- for (i = (rar_entries - a->mc_addr_in_rar_count);
|
|
|
- i < rar_entries; i++)
|
|
|
- ixgbe_enable_rar(hw, i);
|
|
|
-
|
|
|
if (a->mta_in_use > 0)
|
|
|
IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
|
|
|
hw->mac.mc_filter_type);
|
|
|
@@ -1648,15 +1507,8 @@ s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
|
|
|
**/
|
|
|
s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
|
|
|
{
|
|
|
- u32 i;
|
|
|
- u32 rar_entries = hw->mac.num_rar_entries;
|
|
|
struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
|
|
|
|
|
|
- if (a->mc_addr_in_rar_count > 0)
|
|
|
- for (i = (rar_entries - a->mc_addr_in_rar_count);
|
|
|
- i < rar_entries; i++)
|
|
|
- ixgbe_disable_rar(hw, i);
|
|
|
-
|
|
|
if (a->mta_in_use > 0)
|
|
|
IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
|
|
|
|
|
|
@@ -1703,7 +1555,9 @@ s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packetbuf_num)
|
|
|
* 2: Tx flow control is enabled (we can send pause frames but
|
|
|
* we do not support receiving pause frames).
|
|
|
* 3: Both Rx and Tx flow control (symmetric) are enabled.
|
|
|
+#ifdef CONFIG_DCB
|
|
|
* 4: Priority Flow Control is enabled.
|
|
|
+#endif
|
|
|
* other: Invalid.
|
|
|
*/
|
|
|
switch (hw->fc.current_mode) {
|
|
|
@@ -2159,10 +2013,16 @@ out:
|
|
|
**/
|
|
|
s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
|
|
|
{
|
|
|
+ struct ixgbe_adapter *adapter = hw->back;
|
|
|
u32 i;
|
|
|
u32 reg_val;
|
|
|
u32 number_of_queues;
|
|
|
- s32 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
|
|
|
+ s32 status = 0;
|
|
|
+ u16 dev_status = 0;
|
|
|
+
|
|
|
+ /* Just jump out if bus mastering is already disabled */
|
|
|
+ if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
|
|
|
+ goto out;
|
|
|
|
|
|
/* Disable the receive unit by stopping each queue */
|
|
|
number_of_queues = hw->mac.max_rx_queues;
|
|
|
@@ -2179,13 +2039,43 @@ s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
|
|
|
IXGBE_WRITE_REG(hw, IXGBE_CTRL, reg_val);
|
|
|
|
|
|
for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
|
|
|
- if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) {
|
|
|
- status = 0;
|
|
|
+ if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
|
|
|
+ goto check_device_status;
|
|
|
+ udelay(100);
|
|
|
+ }
|
|
|
+
|
|
|
+ hw_dbg(hw, "GIO Master Disable bit didn't clear - requesting resets\n");
|
|
|
+ status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Before proceeding, make sure that the PCIe block does not have
|
|
|
+ * transactions pending.
|
|
|
+ */
|
|
|
+check_device_status:
|
|
|
+ for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
|
|
|
+ pci_read_config_word(adapter->pdev, IXGBE_PCI_DEVICE_STATUS,
|
|
|
+ &dev_status);
|
|
|
+ if (!(dev_status & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
|
|
|
break;
|
|
|
- }
|
|
|
udelay(100);
|
|
|
}
|
|
|
|
|
|
+ if (i == IXGBE_PCI_MASTER_DISABLE_TIMEOUT)
|
|
|
+ hw_dbg(hw, "PCIe transaction pending bit also did not clear.\n");
|
|
|
+ else
|
|
|
+ goto out;
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Two consecutive resets are required via CTRL.RST per datasheet
|
|
|
+ * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
|
|
|
+ * of this need. The first reset prevents new master requests from
|
|
|
+ * being issued by our device. We then must wait 1usec for any
|
|
|
+ * remaining completions from the PCIe bus to trickle in, and then reset
|
|
|
+ * again to clear out any effects they may have had on our device.
|
|
|
+ */
|
|
|
+ hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
|
|
|
+
|
|
|
+out:
|
|
|
return status;
|
|
|
}
|
|
|
|
|
|
@@ -2206,6 +2096,10 @@ s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
|
|
|
s32 timeout = 200;
|
|
|
|
|
|
while (timeout) {
|
|
|
+ /*
|
|
|
+ * SW EEPROM semaphore bit is used for access to all
|
|
|
+ * SW_FW_SYNC/GSSR bits (not just EEPROM)
|
|
|
+ */
|
|
|
if (ixgbe_get_eeprom_semaphore(hw))
|
|
|
return IXGBE_ERR_SWFW_SYNC;
|
|
|
|
|
|
@@ -2223,7 +2117,7 @@ s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
|
|
|
}
|
|
|
|
|
|
if (!timeout) {
|
|
|
- hw_dbg(hw, "Driver can't access resource, GSSR timeout.\n");
|
|
|
+ hw_dbg(hw, "Driver can't access resource, SW_FW_SYNC timeout.\n");
|
|
|
return IXGBE_ERR_SWFW_SYNC;
|
|
|
}
|
|
|
|
|
|
@@ -2427,37 +2321,38 @@ s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
|
|
|
u32 mpsar_lo, mpsar_hi;
|
|
|
u32 rar_entries = hw->mac.num_rar_entries;
|
|
|
|
|
|
- if (rar < rar_entries) {
|
|
|
- mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
|
|
|
- mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
|
|
|
+ /* Make sure we are using a valid rar index range */
|
|
|
+ if (rar >= rar_entries) {
|
|
|
+ hw_dbg(hw, "RAR index %d is out of range.\n", rar);
|
|
|
+ return IXGBE_ERR_INVALID_ARGUMENT;
|
|
|
+ }
|
|
|
|
|
|
- if (!mpsar_lo && !mpsar_hi)
|
|
|
- goto done;
|
|
|
+ mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
|
|
|
+ mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
|
|
|
|
|
|
- if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
|
|
|
- if (mpsar_lo) {
|
|
|
- IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
|
|
|
- mpsar_lo = 0;
|
|
|
- }
|
|
|
- if (mpsar_hi) {
|
|
|
- IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
|
|
|
- mpsar_hi = 0;
|
|
|
- }
|
|
|
- } else if (vmdq < 32) {
|
|
|
- mpsar_lo &= ~(1 << vmdq);
|
|
|
- IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
|
|
|
- } else {
|
|
|
- mpsar_hi &= ~(1 << (vmdq - 32));
|
|
|
- IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
|
|
|
- }
|
|
|
+ if (!mpsar_lo && !mpsar_hi)
|
|
|
+ goto done;
|
|
|
|
|
|
- /* was that the last pool using this rar? */
|
|
|
- if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
|
|
|
- hw->mac.ops.clear_rar(hw, rar);
|
|
|
+ if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
|
|
|
+ if (mpsar_lo) {
|
|
|
+ IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
|
|
|
+ mpsar_lo = 0;
|
|
|
+ }
|
|
|
+ if (mpsar_hi) {
|
|
|
+ IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
|
|
|
+ mpsar_hi = 0;
|
|
|
+ }
|
|
|
+ } else if (vmdq < 32) {
|
|
|
+ mpsar_lo &= ~(1 << vmdq);
|
|
|
+ IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
|
|
|
} else {
|
|
|
- hw_dbg(hw, "RAR index %d is out of range.\n", rar);
|
|
|
+ mpsar_hi &= ~(1 << (vmdq - 32));
|
|
|
+ IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
|
|
|
}
|
|
|
|
|
|
+ /* was that the last pool using this rar? */
|
|
|
+ if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
|
|
|
+ hw->mac.ops.clear_rar(hw, rar);
|
|
|
done:
|
|
|
return 0;
|
|
|
}
|
|
|
@@ -2473,18 +2368,20 @@ s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
|
|
|
u32 mpsar;
|
|
|
u32 rar_entries = hw->mac.num_rar_entries;
|
|
|
|
|
|
- if (rar < rar_entries) {
|
|
|
- if (vmdq < 32) {
|
|
|
- mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
|
|
|
- mpsar |= 1 << vmdq;
|
|
|
- IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
|
|
|
- } else {
|
|
|
- mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
|
|
|
- mpsar |= 1 << (vmdq - 32);
|
|
|
- IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
|
|
|
- }
|
|
|
- } else {
|
|
|
+ /* Make sure we are using a valid rar index range */
|
|
|
+ if (rar >= rar_entries) {
|
|
|
hw_dbg(hw, "RAR index %d is out of range.\n", rar);
|
|
|
+ return IXGBE_ERR_INVALID_ARGUMENT;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (vmdq < 32) {
|
|
|
+ mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
|
|
|
+ mpsar |= 1 << vmdq;
|
|
|
+ IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
|
|
|
+ } else {
|
|
|
+ mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
|
|
|
+ mpsar |= 1 << (vmdq - 32);
|
|
|
+ IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
|
|
|
}
|
|
|
return 0;
|
|
|
}
|
|
|
@@ -2497,7 +2394,6 @@ s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
|
|
|
{
|
|
|
int i;
|
|
|
|
|
|
-
|
|
|
for (i = 0; i < 128; i++)
|
|
|
IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
|
|
|
|
|
|
@@ -2726,12 +2622,21 @@ s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
|
|
|
* Reads the links register to determine if link is up and the current speed
|
|
|
**/
|
|
|
s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
|
|
|
- bool *link_up, bool link_up_wait_to_complete)
|
|
|
+ bool *link_up, bool link_up_wait_to_complete)
|
|
|
{
|
|
|
- u32 links_reg;
|
|
|
+ u32 links_reg, links_orig;
|
|
|
u32 i;
|
|
|
|
|
|
+ /* clear the old state */
|
|
|
+ links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
|
|
|
+
|
|
|
links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
|
|
|
+
|
|
|
+ if (links_orig != links_reg) {
|
|
|
+ hw_dbg(hw, "LINKS changed from %08X to %08X\n",
|
|
|
+ links_orig, links_reg);
|
|
|
+ }
|
|
|
+
|
|
|
if (link_up_wait_to_complete) {
|
|
|
for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
|
|
|
if (links_reg & IXGBE_LINKS_UP) {
|
|
|
@@ -2754,10 +2659,13 @@ s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
|
|
|
IXGBE_LINKS_SPEED_10G_82599)
|
|
|
*speed = IXGBE_LINK_SPEED_10GB_FULL;
|
|
|
else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
|
|
|
- IXGBE_LINKS_SPEED_1G_82599)
|
|
|
+ IXGBE_LINKS_SPEED_1G_82599)
|
|
|
*speed = IXGBE_LINK_SPEED_1GB_FULL;
|
|
|
- else
|
|
|
+ else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
|
|
|
+ IXGBE_LINKS_SPEED_100_82599)
|
|
|
*speed = IXGBE_LINK_SPEED_100_FULL;
|
|
|
+ else
|
|
|
+ *speed = IXGBE_LINK_SPEED_UNKNOWN;
|
|
|
|
|
|
/* if link is down, zero out the current_mode */
|
|
|
if (*link_up == false) {
|
David S. Miller