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+/*
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+ * Marvell EBU SoC common clock handling
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+ *
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+ * Copyright (C) 2012 Marvell
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+ *
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+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
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+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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+ * Andrew Lunn <andrew@lunn.ch>
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+ *
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+ * This file is licensed under the terms of the GNU General Public
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+ * License version 2. This program is licensed "as is" without any
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+ * warranty of any kind, whether express or implied.
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+ */
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+
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+#include <linux/kernel.h>
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+#include <linux/clk.h>
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+#include <linux/clkdev.h>
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+#include <linux/clk-provider.h>
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+#include <linux/io.h>
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+#include <linux/of.h>
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+#include <linux/of_address.h>
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+
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+#include "common.h"
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+
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+/*
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+ * Core Clocks
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+ */
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+
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+static struct clk_onecell_data clk_data;
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+
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+void __init mvebu_coreclk_setup(struct device_node *np,
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+ const struct coreclk_soc_desc *desc)
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+{
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+ const char *tclk_name = "tclk";
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+ const char *cpuclk_name = "cpuclk";
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+ void __iomem *base;
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+ unsigned long rate;
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+ int n;
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+
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+ base = of_iomap(np, 0);
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+ if (WARN_ON(!base))
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+ return;
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+
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+ /* Allocate struct for TCLK, cpu clk, and core ratio clocks */
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+ clk_data.clk_num = 2 + desc->num_ratios;
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+ clk_data.clks = kzalloc(clk_data.clk_num * sizeof(struct clk *),
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+ GFP_KERNEL);
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+ if (WARN_ON(!clk_data.clks))
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+ return;
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+
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+ /* Register TCLK */
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+ of_property_read_string_index(np, "clock-output-names", 0,
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+ &tclk_name);
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+ rate = desc->get_tclk_freq(base);
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+ clk_data.clks[0] = clk_register_fixed_rate(NULL, tclk_name, NULL,
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+ CLK_IS_ROOT, rate);
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+ WARN_ON(IS_ERR(clk_data.clks[0]));
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+
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+ /* Register CPU clock */
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+ of_property_read_string_index(np, "clock-output-names", 1,
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+ &cpuclk_name);
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+ rate = desc->get_cpu_freq(base);
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+ clk_data.clks[1] = clk_register_fixed_rate(NULL, cpuclk_name, NULL,
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+ CLK_IS_ROOT, rate);
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+ WARN_ON(IS_ERR(clk_data.clks[1]));
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+
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+ /* Register fixed-factor clocks derived from CPU clock */
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+ for (n = 0; n < desc->num_ratios; n++) {
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+ const char *rclk_name = desc->ratios[n].name;
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+ int mult, div;
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+
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+ of_property_read_string_index(np, "clock-output-names",
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+ 2+n, &rclk_name);
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+ desc->get_clk_ratio(base, desc->ratios[n].id, &mult, &div);
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+ clk_data.clks[2+n] = clk_register_fixed_factor(NULL, rclk_name,
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+ cpuclk_name, 0, mult, div);
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+ WARN_ON(IS_ERR(clk_data.clks[2+n]));
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+ };
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+
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+ /* SAR register isn't needed anymore */
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+ iounmap(base);
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+
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+ of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
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+}
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+
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+/*
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+ * Clock Gating Control
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+ */
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+
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+struct clk_gating_ctrl {
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+ spinlock_t lock;
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+ struct clk **gates;
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+ int num_gates;
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+};
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+
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+#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
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+
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+static struct clk *clk_gating_get_src(
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+ struct of_phandle_args *clkspec, void *data)
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+{
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+ struct clk_gating_ctrl *ctrl = (struct clk_gating_ctrl *)data;
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+ int n;
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+
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+ if (clkspec->args_count < 1)
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+ return ERR_PTR(-EINVAL);
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+
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+ for (n = 0; n < ctrl->num_gates; n++) {
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+ struct clk_gate *gate =
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+ to_clk_gate(__clk_get_hw(ctrl->gates[n]));
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+ if (clkspec->args[0] == gate->bit_idx)
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+ return ctrl->gates[n];
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+ }
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+ return ERR_PTR(-ENODEV);
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+}
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+
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+void __init mvebu_clk_gating_setup(struct device_node *np,
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+ const struct clk_gating_soc_desc *desc)
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+{
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+ struct clk_gating_ctrl *ctrl;
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+ struct clk *clk;
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+ void __iomem *base;
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+ const char *default_parent = NULL;
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+ int n;
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+
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+ base = of_iomap(np, 0);
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+ if (WARN_ON(!base))
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+ return;
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+
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+ clk = of_clk_get(np, 0);
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+ if (!IS_ERR(clk)) {
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+ default_parent = __clk_get_name(clk);
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+ clk_put(clk);
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+ }
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+
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+ ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
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+ if (WARN_ON(!ctrl))
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+ return;
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+
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+ spin_lock_init(&ctrl->lock);
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+
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+ /* Count, allocate, and register clock gates */
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+ for (n = 0; desc[n].name;)
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+ n++;
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+
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+ ctrl->num_gates = n;
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+ ctrl->gates = kzalloc(ctrl->num_gates * sizeof(struct clk *),
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+ GFP_KERNEL);
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+ if (WARN_ON(!ctrl->gates)) {
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+ kfree(ctrl);
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+ return;
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+ }
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+
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+ for (n = 0; n < ctrl->num_gates; n++) {
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+ const char *parent =
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+ (desc[n].parent) ? desc[n].parent : default_parent;
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+ ctrl->gates[n] = clk_register_gate(NULL, desc[n].name, parent,
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+ desc[n].flags, base, desc[n].bit_idx,
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+ 0, &ctrl->lock);
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+ WARN_ON(IS_ERR(ctrl->gates[n]));
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+ }
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+
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+ of_clk_add_provider(np, clk_gating_get_src, ctrl);
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+}
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