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@@ -206,6 +206,8 @@ union hsw_tsx_tuning {
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u64 value;
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};
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+#define PEBS_HSW_TSX_FLAGS 0xff00000000ULL
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+
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void init_debug_store_on_cpu(int cpu)
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{
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struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
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@@ -807,6 +809,16 @@ static inline u64 intel_hsw_weight(struct pebs_record_hsw *pebs)
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return 0;
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}
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+static inline u64 intel_hsw_transaction(struct pebs_record_hsw *pebs)
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+{
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+ u64 txn = (pebs->tsx_tuning & PEBS_HSW_TSX_FLAGS) >> 32;
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+
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+ /* For RTM XABORTs also log the abort code from AX */
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+ if ((txn & PERF_TXN_TRANSACTION) && (pebs->ax & 1))
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+ txn |= ((pebs->ax >> 24) & 0xff) << PERF_TXN_ABORT_SHIFT;
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+ return txn;
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+}
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+
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static void __intel_pmu_pebs_event(struct perf_event *event,
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struct pt_regs *iregs, void *__pebs)
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{
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@@ -885,10 +897,14 @@ static void __intel_pmu_pebs_event(struct perf_event *event,
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x86_pmu.intel_cap.pebs_format >= 1)
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data.addr = pebs->dla;
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- /* Only set the TSX weight when no memory weight was requested. */
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- if ((event->attr.sample_type & PERF_SAMPLE_WEIGHT) && !fll &&
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- (x86_pmu.intel_cap.pebs_format >= 2))
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- data.weight = intel_hsw_weight(pebs);
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+ if (x86_pmu.intel_cap.pebs_format >= 2) {
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+ /* Only set the TSX weight when no memory weight. */
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+ if ((event->attr.sample_type & PERF_SAMPLE_WEIGHT) && !fll)
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+ data.weight = intel_hsw_weight(pebs);
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+
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+ if (event->attr.sample_type & PERF_SAMPLE_TRANSACTION)
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+ data.txn = intel_hsw_transaction(pebs);
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+ }
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if (has_branch_stack(event))
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data.br_stack = &cpuc->lbr_stack;
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