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@@ -174,7 +174,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
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switch (freq) {
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case 83:
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- min_gpmc_clk_period = 12; /* 83 MHz */
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+ min_gpmc_clk_period = 12000; /* 83 MHz */
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t_ces = 5;
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t_avds = 4;
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t_avdh = 2;
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@@ -183,7 +183,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
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t_rdyo = 9;
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break;
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case 66:
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- min_gpmc_clk_period = 15; /* 66 MHz */
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+ min_gpmc_clk_period = 15000; /* 66 MHz */
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t_ces = 6;
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t_avds = 5;
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t_avdh = 2;
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@@ -192,7 +192,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
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t_rdyo = 11;
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break;
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default:
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- min_gpmc_clk_period = 18; /* 54 MHz */
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+ min_gpmc_clk_period = 18500; /* 54 MHz */
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t_ces = 7;
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t_avds = 7;
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t_avdh = 7;
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@@ -271,8 +271,8 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
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t.wr_cycle = t.rd_cycle;
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if (cpu_is_omap34xx()) {
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t.wr_data_mux_bus = gpmc_ticks_to_ns(fclk_offset +
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- gpmc_ns_to_ticks(min_gpmc_clk_period +
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- t_rdyo));
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+ gpmc_ps_to_ticks(min_gpmc_clk_period +
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+ t_rdyo * 1000));
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t.wr_access = t.access;
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}
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} else {
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