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@@ -399,7 +399,7 @@ void _rxadc_dc_offset_cancellation_winbond(struct hw_data *phw_data, u32 frequen
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val |= MASK_ADC_DC_CAL_STR;
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hw_set_dxx_reg(phw_data, REG_MODE_CTRL, val);
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- /* e. The result are shown in "adc_dc_cal_i[8:0] and adc_dc_cal_q[8:0]" */
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+ /* e. The results are shown in "adc_dc_cal_i[8:0] and adc_dc_cal_q[8:0]" */
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#ifdef _DEBUG
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hw_get_dxx_reg(phw_data, REG_OFFSET_READ, &val);
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PHY_DEBUG(("[CAL] REG_OFFSET_READ = 0x%08X\n", val));
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@@ -720,7 +720,7 @@ u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data,
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for (capture_time = 0; capture_time < 10; capture_time++) {
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/*
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* a. Set iqcal_mode[1:0] to 0x2 and set "calib_start" to 0x1 to
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- * enable "IQ alibration Mode II"
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+ * enable "IQ calibration Mode II"
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*/
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reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE);
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reg_mode_ctrl &= ~MASK_IQCAL_MODE;
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@@ -750,7 +750,7 @@ u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data,
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/*
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* d. Set iqcal_mode[1:0] to 0x3 and set "calib_start" to 0x1 to
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- * enable "IQ alibration Mode II"
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+ * enable "IQ calibration Mode II"
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*/
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/* hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &val); */
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hw_get_dxx_reg(phw_data, REG_MODE_CTRL, ®_mode_ctrl);
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@@ -980,7 +980,7 @@ void _tx_iq_calibration_winbond(struct hw_data *phw_data)
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phy_set_rf_data(phw_data, 0, (0<<24)|0xFDF1C0);
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/* ; [BB-chip]: Calibration (6f).Send test pattern */
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/* ; [BB-chip]: Calibration (6g). Search RXGCL optimal value */
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- /* ; [BB-chip]: Calibration (6h). Caculate TX-path IQ imbalance and setting TX path IQ compensation table */
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+ /* ; [BB-chip]: Calibration (6h). Calculate TX-path IQ imbalance and setting TX path IQ compensation table */
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/* phy_set_rf_data(phw_data, 3, (3<<24)|0x025586); */
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msleep(30); /* 20060612.1.a 30ms delay. Add the follow 2 lines */
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@@ -1373,7 +1373,7 @@ u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 fre
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/***************************************************************/
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void _rx_iq_calibration_winbond(struct hw_data *phw_data, u32 frequency)
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{
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-/* figo 20050523 marked this flag for can't compile for relesase */
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+/* figo 20050523 marked this flag for can't compile for release */
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#ifdef _DEBUG
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s32 rx_cal_reg[4];
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u32 val;
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@@ -1397,7 +1397,7 @@ void _rx_iq_calibration_winbond(struct hw_data *phw_data, u32 frequency)
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/* ; [BB-chip]: Calibration (7f). Send test pattern */
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/* ; [BB-chip]: Calibration (7g). Search RXGCL optimal value */
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- /* ; [BB-chip]: Calibration (7h). Caculate RX-path IQ imbalance and setting RX path IQ compensation table */
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+ /* ; [BB-chip]: Calibration (7h). Calculate RX-path IQ imbalance and setting RX path IQ compensation table */
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result = _rx_iq_calibration_loop_winbond(phw_data, 12589, frequency);
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@@ -1454,7 +1454,7 @@ void phy_calibration_winbond(struct hw_data *phw_data, u32 frequency)
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_rxadc_dc_offset_cancellation_winbond(phw_data, frequency);
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/* _txidac_dc_offset_cancellation_winbond(phw_data); */
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- /* _txqdac_dc_offset_cacellation_winbond(phw_data); */
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+ /* _txqdac_dc_offset_cancellation_winbond(phw_data); */
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_tx_iq_calibration_winbond(phw_data);
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_rx_iq_calibration_winbond(phw_data, frequency);
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