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@@ -281,27 +281,9 @@ pcibios_fixup_device_resources(struct pci_dev *dev, struct pci_bus *bus)
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void __devinit
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pcibios_fixup_bus(struct pci_bus *bus)
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{
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- /* Propagate hose info into the subordinate devices. */
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-
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- struct pci_controller *hose = bus->sysdata;
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struct pci_dev *dev = bus->self;
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- if (!dev) {
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- /* Root bus. */
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- u32 pci_mem_end;
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- u32 sg_base = hose->sg_pci ? hose->sg_pci->dma_base : ~0;
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- unsigned long end;
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-
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- bus->resource[0] = hose->io_space;
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- bus->resource[1] = hose->mem_space;
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-
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- /* Adjust hose mem_space limit to prevent PCI allocations
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- in the iommu windows. */
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- pci_mem_end = min((u32)__direct_map_base, sg_base) - 1;
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- end = hose->mem_space->start + pci_mem_end;
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- if (hose->mem_space->end > end)
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- hose->mem_space->end = end;
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- } else if (pci_probe_only &&
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+ if (pci_probe_only && dev &&
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(dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
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pci_read_bridge_bases(bus);
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pcibios_fixup_device_resources(dev, bus);
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@@ -414,13 +396,31 @@ void __init
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common_init_pci(void)
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{
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struct pci_controller *hose;
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+ struct list_head resources;
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struct pci_bus *bus;
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int next_busno;
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int need_domain_info = 0;
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+ u32 pci_mem_end;
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+ u32 sg_base;
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+ unsigned long end;
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/* Scan all of the recorded PCI controllers. */
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for (next_busno = 0, hose = hose_head; hose; hose = hose->next) {
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- bus = pci_scan_bus(next_busno, alpha_mv.pci_ops, hose);
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+ sg_base = hose->sg_pci ? hose->sg_pci->dma_base : ~0;
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+
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+ /* Adjust hose mem_space limit to prevent PCI allocations
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+ in the iommu windows. */
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+ pci_mem_end = min((u32)__direct_map_base, sg_base) - 1;
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+ end = hose->mem_space->start + pci_mem_end;
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+ if (hose->mem_space->end > end)
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+ hose->mem_space->end = end;
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+
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+ INIT_LIST_HEAD(&resources);
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+ pci_add_resource(&resources, hose->io_space);
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+ pci_add_resource(&resources, hose->mem_space);
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+
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+ bus = pci_scan_root_bus(NULL, next_busno, alpha_mv.pci_ops,
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+ hose, &resources);
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hose->bus = bus;
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hose->need_domain_info = need_domain_info;
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next_busno = bus->subordinate + 1;
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