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@@ -600,14 +600,16 @@ void i915_save_display(struct drm_device *dev)
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}
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/* FIXME: save TV & SDVO state */
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- /* FBC state */
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- if (IS_GM45(dev)) {
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- dev_priv->saveDPFC_CB_BASE = I915_READ(DPFC_CB_BASE);
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- } else {
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- dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
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- dev_priv->saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
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- dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
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- dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL);
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+ /* Only save FBC state on the platform that supports FBC */
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+ if (I915_HAS_FBC(dev)) {
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+ if (IS_GM45(dev)) {
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+ dev_priv->saveDPFC_CB_BASE = I915_READ(DPFC_CB_BASE);
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+ } else {
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+ dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
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+ dev_priv->saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
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+ dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
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+ dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL);
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+ }
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}
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/* VGA state */
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@@ -702,18 +704,19 @@ void i915_restore_display(struct drm_device *dev)
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}
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/* FIXME: restore TV & SDVO state */
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- /* FBC info */
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- if (IS_GM45(dev)) {
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- g4x_disable_fbc(dev);
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- I915_WRITE(DPFC_CB_BASE, dev_priv->saveDPFC_CB_BASE);
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- } else {
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- i8xx_disable_fbc(dev);
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- I915_WRITE(FBC_CFB_BASE, dev_priv->saveFBC_CFB_BASE);
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- I915_WRITE(FBC_LL_BASE, dev_priv->saveFBC_LL_BASE);
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- I915_WRITE(FBC_CONTROL2, dev_priv->saveFBC_CONTROL2);
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- I915_WRITE(FBC_CONTROL, dev_priv->saveFBC_CONTROL);
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+ /* only restore FBC info on the platform that supports FBC*/
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+ if (I915_HAS_FBC(dev)) {
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+ if (IS_GM45(dev)) {
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+ g4x_disable_fbc(dev);
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+ I915_WRITE(DPFC_CB_BASE, dev_priv->saveDPFC_CB_BASE);
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+ } else {
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+ i8xx_disable_fbc(dev);
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+ I915_WRITE(FBC_CFB_BASE, dev_priv->saveFBC_CFB_BASE);
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+ I915_WRITE(FBC_LL_BASE, dev_priv->saveFBC_LL_BASE);
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+ I915_WRITE(FBC_CONTROL2, dev_priv->saveFBC_CONTROL2);
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+ I915_WRITE(FBC_CONTROL, dev_priv->saveFBC_CONTROL);
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+ }
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}
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-
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/* VGA state */
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if (IS_IRONLAKE(dev))
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I915_WRITE(CPU_VGACNTRL, dev_priv->saveVGACNTRL);
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