|
@@ -32,7 +32,7 @@ BARRIER IO before the access to the SMC chip because the AEN latch
|
|
|
only needs occurs after the SMC IO write cycle. The routines that
|
|
|
implement this work-around make an additional concession which is to
|
|
|
disable interrupts during the IO sequence. Other hardware devices
|
|
|
-(the LogicPD CPLD) have registers in the same the physical memory
|
|
|
+(the LogicPD CPLD) have registers in the same physical memory
|
|
|
region as the SMC chip. An interrupt might allow an access to one of
|
|
|
those registers while SMC IO is being performed.
|
|
|
|