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@@ -52,27 +52,27 @@ static int omap2_nand_gpmc_retime(
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memset(&t, 0, sizeof(t));
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t.sync_clk = gpmc_t->sync_clk;
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- t.cs_on = gpmc_round_ns_to_ticks(gpmc_t->cs_on);
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- t.adv_on = gpmc_round_ns_to_ticks(gpmc_t->adv_on);
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+ t.cs_on = gpmc_t->cs_on;
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+ t.adv_on = gpmc_t->adv_on;
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/* Read */
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- t.adv_rd_off = gpmc_round_ns_to_ticks(gpmc_t->adv_rd_off);
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+ t.adv_rd_off = gpmc_t->adv_rd_off;
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t.oe_on = t.adv_on;
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- t.access = gpmc_round_ns_to_ticks(gpmc_t->access);
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- t.oe_off = gpmc_round_ns_to_ticks(gpmc_t->oe_off);
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- t.cs_rd_off = gpmc_round_ns_to_ticks(gpmc_t->cs_rd_off);
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- t.rd_cycle = gpmc_round_ns_to_ticks(gpmc_t->rd_cycle);
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+ t.access = gpmc_t->access;
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+ t.oe_off = gpmc_t->oe_off;
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+ t.cs_rd_off = gpmc_t->cs_rd_off;
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+ t.rd_cycle = gpmc_t->rd_cycle;
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/* Write */
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- t.adv_wr_off = gpmc_round_ns_to_ticks(gpmc_t->adv_wr_off);
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+ t.adv_wr_off = gpmc_t->adv_wr_off;
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t.we_on = t.oe_on;
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if (cpu_is_omap34xx()) {
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- t.wr_data_mux_bus = gpmc_round_ns_to_ticks(gpmc_t->wr_data_mux_bus);
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- t.wr_access = gpmc_round_ns_to_ticks(gpmc_t->wr_access);
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+ t.wr_data_mux_bus = gpmc_t->wr_data_mux_bus;
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+ t.wr_access = gpmc_t->wr_access;
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}
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- t.we_off = gpmc_round_ns_to_ticks(gpmc_t->we_off);
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- t.cs_wr_off = gpmc_round_ns_to_ticks(gpmc_t->cs_wr_off);
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- t.wr_cycle = gpmc_round_ns_to_ticks(gpmc_t->wr_cycle);
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+ t.we_off = gpmc_t->we_off;
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+ t.cs_wr_off = gpmc_t->cs_wr_off;
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+ t.wr_cycle = gpmc_t->wr_cycle;
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/* Configure GPMC */
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if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16)
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