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@@ -223,15 +223,31 @@ int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
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return 0;
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return 0;
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}
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}
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+int rs400_mc_wait_for_idle(struct radeon_device *rdev)
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+{
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+ unsigned i;
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+ uint32_t tmp;
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+
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+ for (i = 0; i < rdev->usec_timeout; i++) {
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+ /* read MC_STATUS */
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+ tmp = RREG32(0x0150);
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+ if (tmp & (1 << 2)) {
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+ return 0;
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+ }
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+ DRM_UDELAY(1);
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+ }
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+ return -1;
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+}
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+
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void rs400_gpu_init(struct radeon_device *rdev)
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void rs400_gpu_init(struct radeon_device *rdev)
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{
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{
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/* FIXME: HDP same place on rs400 ? */
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/* FIXME: HDP same place on rs400 ? */
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r100_hdp_reset(rdev);
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r100_hdp_reset(rdev);
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/* FIXME: is this correct ? */
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/* FIXME: is this correct ? */
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r420_pipes_init(rdev);
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r420_pipes_init(rdev);
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- if (r300_mc_wait_for_idle(rdev)) {
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- printk(KERN_WARNING "Failed to wait MC idle while "
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- "programming pipes. Bad things might happen.\n");
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+ if (rs400_mc_wait_for_idle(rdev)) {
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+ printk(KERN_WARNING "rs400: Failed to wait MC idle while "
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+ "programming pipes. Bad things might happen. %08x\n", RREG32(0x150));
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}
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}
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}
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}
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@@ -370,8 +386,8 @@ void rs400_mc_program(struct radeon_device *rdev)
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r100_mc_stop(rdev, &save);
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r100_mc_stop(rdev, &save);
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/* Wait for mc idle */
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/* Wait for mc idle */
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- if (r300_mc_wait_for_idle(rdev))
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- dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
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+ if (rs400_mc_wait_for_idle(rdev))
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+ dev_warn(rdev->dev, "rs400: Wait MC idle timeout before updating MC.\n");
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WREG32(R_000148_MC_FB_LOCATION,
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WREG32(R_000148_MC_FB_LOCATION,
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S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
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S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
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S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
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S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
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