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@@ -861,7 +861,7 @@ static void ath9k_hw_9271_pa_cal(struct ath_hw *ah)
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REG_WRITE(ah, regList[i][0], regList[i][1]);
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}
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-static inline void ath9k_hw_9285_pa_cal(struct ath_hw *ah)
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+static inline void ath9k_hw_9285_pa_cal(struct ath_hw *ah, bool is_reset)
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{
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u32 regVal;
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@@ -877,6 +877,8 @@ static inline void ath9k_hw_9285_pa_cal(struct ath_hw *ah)
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{ 0x7838, 0 },
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};
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+ DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "Running PA Calibration\n");
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+
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if (AR_SREV_9285_11(ah)) {
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REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14));
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udelay(10);
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@@ -936,6 +938,17 @@ static inline void ath9k_hw_9285_pa_cal(struct ath_hw *ah)
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offs_6_1 = offset>>1;
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offs_0 = offset & 1;
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+ if ((!is_reset) && (ah->pacal_info.prev_offset == offset)) {
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+ if (ah->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT)
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+ ah->pacal_info.max_skipcount =
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+ 2 * ah->pacal_info.max_skipcount;
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+ ah->pacal_info.skipcount = ah->pacal_info.max_skipcount;
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+ } else {
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+ ah->pacal_info.max_skipcount = 1;
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+ ah->pacal_info.skipcount = 0;
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+ ah->pacal_info.prev_offset = offset;
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+ }
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+
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REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, offs_6_1);
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REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, offs_0);
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@@ -982,8 +995,12 @@ bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan,
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/* Do periodic PAOffset Cal */
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if (AR_SREV_9271(ah))
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ath9k_hw_9271_pa_cal(ah);
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- else if (AR_SREV_9285_11_OR_LATER(ah))
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- ath9k_hw_9285_pa_cal(ah);
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+ else if (AR_SREV_9285_11_OR_LATER(ah)) {
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+ if (!ah->pacal_info.skipcount)
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+ ath9k_hw_9285_pa_cal(ah, false);
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+ else
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+ ah->pacal_info.skipcount--;
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+ }
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if (OLC_FOR_AR9280_20_LATER || OLC_FOR_AR9287_10_LATER)
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ath9k_olc_temp_compensation(ah);
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@@ -1081,7 +1098,7 @@ bool ath9k_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
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/* Do PA Calibration */
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if (AR_SREV_9285_11_OR_LATER(ah))
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- ath9k_hw_9285_pa_cal(ah);
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+ ath9k_hw_9285_pa_cal(ah, true);
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/* Do NF Calibration after DC offset and other calibrations */
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REG_WRITE(ah, AR_PHY_AGC_CONTROL,
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