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@@ -1111,14 +1111,19 @@ static void bnx2x_hc_int_enable(struct bnx2x *bp)
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HC_CONFIG_0_REG_INT_LINE_EN_0 |
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HC_CONFIG_0_REG_ATTN_BIT_EN_0);
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- DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
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- val, port, addr);
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+ if (!CHIP_IS_E1(bp)) {
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+ DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
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+ val, port, addr);
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- REG_WR(bp, addr, val);
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+ REG_WR(bp, addr, val);
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- val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
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+ val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
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+ }
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}
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+ if (CHIP_IS_E1(bp))
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+ REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
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+
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DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n",
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val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
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@@ -1212,10 +1217,26 @@ static void bnx2x_hc_int_disable(struct bnx2x *bp)
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u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
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u32 val = REG_RD(bp, addr);
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- val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
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- HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
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- HC_CONFIG_0_REG_INT_LINE_EN_0 |
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- HC_CONFIG_0_REG_ATTN_BIT_EN_0);
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+ /*
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+ * in E1 we must use only PCI configuration space to disable
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+ * MSI/MSIX capablility
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+ * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
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+ */
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+ if (CHIP_IS_E1(bp)) {
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+ /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
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+ * Use mask register to prevent from HC sending interrupts
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+ * after we exit the function
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+ */
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+ REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
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+
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+ val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
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+ HC_CONFIG_0_REG_INT_LINE_EN_0 |
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+ HC_CONFIG_0_REG_ATTN_BIT_EN_0);
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+ } else
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+ val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
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+ HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
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+ HC_CONFIG_0_REG_INT_LINE_EN_0 |
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+ HC_CONFIG_0_REG_ATTN_BIT_EN_0);
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DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
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val, port, addr);
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