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@@ -50,6 +50,7 @@ enum {
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AHCI_CMD_SLOT_SZ = 32 * 32,
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AHCI_RX_FIS_SZ = 256,
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AHCI_CMD_TBL_HDR = 0x80,
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+ AHCI_CMD_TBL_CDB = 0x40,
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AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16),
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AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_SZ +
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AHCI_RX_FIS_SZ,
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@@ -510,7 +511,8 @@ static void ahci_fill_sg(struct ata_queued_cmd *qc)
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static void ahci_qc_prep(struct ata_queued_cmd *qc)
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{
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- struct ahci_port_priv *pp = qc->ap->private_data;
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+ struct ata_port *ap = qc->ap;
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+ struct ahci_port_priv *pp = ap->private_data;
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u32 opts;
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const u32 cmd_fis_len = 5; /* five dwords */
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@@ -522,18 +524,8 @@ static void ahci_qc_prep(struct ata_queued_cmd *qc)
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opts = (qc->n_elem << 16) | cmd_fis_len;
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if (qc->tf.flags & ATA_TFLAG_WRITE)
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opts |= AHCI_CMD_WRITE;
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-
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- switch (qc->tf.protocol) {
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- case ATA_PROT_ATAPI:
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- case ATA_PROT_ATAPI_NODATA:
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- case ATA_PROT_ATAPI_DMA:
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+ if (is_atapi_taskfile(&qc->tf))
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opts |= AHCI_CMD_ATAPI;
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- break;
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-
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- default:
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- /* do nothing */
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- break;
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- }
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pp->cmd_slot[0].opts = cpu_to_le32(opts);
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pp->cmd_slot[0].status = 0;
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@@ -545,6 +537,10 @@ static void ahci_qc_prep(struct ata_queued_cmd *qc)
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* a SATA Register - Host to Device command FIS.
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*/
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ata_tf_to_fis(&qc->tf, pp->cmd_tbl, 0);
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+ if (opts & AHCI_CMD_ATAPI) {
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+ memset(pp->cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
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+ memcpy(pp->cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, ap->cdb_len);
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+ }
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if (!(qc->flags & ATA_QCFLAG_DMAMAP))
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return;
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