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@@ -1718,14 +1718,13 @@
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GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
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GEN7_CXT_GT1_SIZE(ctx_reg) + \
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GEN7_CXT_VFSTATE_SIZE(ctx_reg))
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-#define HSW_CXT_POWER_SIZE(ctx_reg) ((ctx_reg >> 26) & 0x3f)
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-#define HSW_CXT_RING_SIZE(ctx_reg) ((ctx_reg >> 23) & 0x7)
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-#define HSW_CXT_RENDER_SIZE(ctx_reg) ((ctx_reg >> 15) & 0xff)
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-#define HSW_CXT_TOTAL_SIZE(ctx_reg) (HSW_CXT_POWER_SIZE(ctx_reg) + \
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- HSW_CXT_RING_SIZE(ctx_reg) + \
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- HSW_CXT_RENDER_SIZE(ctx_reg) + \
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- GEN7_CXT_VFSTATE_SIZE(ctx_reg))
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-
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+/* Haswell does have the CXT_SIZE register however it does not appear to be
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+ * valid. Now, docs explain in dwords what is in the context object. The full
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+ * size is 70720 bytes, however, the power context and execlist context will
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+ * never be saved (power context is stored elsewhere, and execlists don't work
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+ * on HSW) - so the final size is 66944 bytes, which rounds to 17 pages.
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+ */
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+#define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE)
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/*
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* Overlay regs
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