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@@ -73,7 +73,7 @@ static DEFINE_SPINLOCK(efar_lock);
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/**
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* efar_set_piomode - Initialize host controller PATA PIO timings
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* @ap: Port whose timings we are configuring
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- * @adev: um
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+ * @adev: Device to program
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*
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* Set PIO mode for device, in host controller PCI config space.
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*
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@@ -85,9 +85,9 @@ static void efar_set_piomode (struct ata_port *ap, struct ata_device *adev)
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{
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unsigned int pio = adev->pio_mode - XFER_PIO_0;
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struct pci_dev *dev = to_pci_dev(ap->host->dev);
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- unsigned int idetm_port= ap->port_no ? 0x42 : 0x40;
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+ unsigned int master_port = ap->port_no ? 0x42 : 0x40;
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unsigned long flags;
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- u16 idetm_data;
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+ u16 master_data;
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u8 udma_enable;
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int control = 0;
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@@ -113,20 +113,20 @@ static void efar_set_piomode (struct ata_port *ap, struct ata_device *adev)
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spin_lock_irqsave(&efar_lock, flags);
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- pci_read_config_word(dev, idetm_port, &idetm_data);
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+ pci_read_config_word(dev, master_port, &master_data);
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/* Set PPE, IE, and TIME as appropriate */
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if (adev->devno == 0) {
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- idetm_data &= 0xCCF0;
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- idetm_data |= control;
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- idetm_data |= (timings[pio][0] << 12) |
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+ master_data &= 0xCCF0;
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+ master_data |= control;
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+ master_data |= (timings[pio][0] << 12) |
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(timings[pio][1] << 8);
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} else {
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int shift = 4 * ap->port_no;
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u8 slave_data;
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- idetm_data &= 0xFF0F;
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- idetm_data |= (control << 4);
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+ master_data &= 0xFF0F;
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+ master_data |= (control << 4);
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/* Slave timing in separate register */
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pci_read_config_byte(dev, 0x44, &slave_data);
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@@ -135,8 +135,8 @@ static void efar_set_piomode (struct ata_port *ap, struct ata_device *adev)
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pci_write_config_byte(dev, 0x44, slave_data);
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}
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- idetm_data |= 0x4000; /* Ensure SITRE is set */
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- pci_write_config_word(dev, idetm_port, idetm_data);
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+ master_data |= 0x4000; /* Ensure SITRE is set */
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+ pci_write_config_word(dev, master_port, master_data);
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pci_read_config_byte(dev, 0x48, &udma_enable);
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udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
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