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ARM: 7291/1: cache: assume 64-byte L1 cachelines for ARMv7 CPUs

To ensure correct alignment of cacheline-aligned data, the maximum
cacheline size needs to be known at compile time.

Since Cortex-A8 and Cortex-A15 have 64-byte cachelines (and it is likely
that there will be future ARMv7 implementations with the same line size)
then it makes sense to assume that CPU_V7 implies a 64-byte L1 cacheline
size. For CPUs with smaller caches, this will result in some harmless
padding but will help with single zImage work and avoid hitting subtle
bugs with misaligned data structures.

Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Will Deacon преди 13 години
родител
972da06470
ревизия
a092f2b153
променени са 4 файла, в които са добавени 1 реда и са изтрити 6 реда
Обединен изглед Покажи статистика за разликите
  1. 0 2
      arch/arm/Kconfig
  2. 0 3
      arch/arm/mach-mx5/Kconfig
  3. 0 1
      arch/arm/mach-omap2/Kconfig
  4. 1 0
      arch/arm/mm/Kconfig

+ 0 - 2
arch/arm/Kconfig
Целия файл 

@@ -825,7 +825,6 @@ config ARCH_S5PC100
 
 	select HAVE_CLK
 
 	select HAVE_CLK
 
 	select CLKDEV_LOOKUP
 
 	select CLKDEV_LOOKUP
 
 	select CPU_V7
 
 	select CPU_V7
 
-	select ARM_L1_CACHE_SHIFT_6
 
 	select ARCH_USES_GETTIMEOFFSET
 
 	select ARCH_USES_GETTIMEOFFSET
 
 	select HAVE_S3C2410_I2C if I2C
 
 	select HAVE_S3C2410_I2C if I2C
 
 	select HAVE_S3C_RTC if RTC_CLASS
 
 	select HAVE_S3C_RTC if RTC_CLASS
 
@@ -842,7 +841,6 @@ config ARCH_S5PV210
 
 	select HAVE_CLK
 
 	select HAVE_CLK
 
 	select CLKDEV_LOOKUP
 
 	select CLKDEV_LOOKUP
 
 	select CLKSRC_MMIO
 
 	select CLKSRC_MMIO
 
-	select ARM_L1_CACHE_SHIFT_6
 
 	select ARCH_HAS_CPUFREQ
 
 	select ARCH_HAS_CPUFREQ
 
 	select GENERIC_CLOCKEVENTS
 
 	select GENERIC_CLOCKEVENTS
 
 	select HAVE_SCHED_CLOCK
 
 	select HAVE_SCHED_CLOCK

+ 0 - 3
arch/arm/mach-mx5/Kconfig
Целия файл 

@@ -15,7 +15,6 @@ config ARCH_MX53
 
 config SOC_IMX50
 
 config SOC_IMX50
 
 	bool
 
 	bool
 
 	select CPU_V7
 
 	select CPU_V7
 
-	select ARM_L1_CACHE_SHIFT_6
 
 	select MXC_TZIC
 
 	select MXC_TZIC
 
 	select ARCH_MXC_IOMUX_V3
 
 	select ARCH_MXC_IOMUX_V3
 
 	select ARCH_MXC_AUDMUX_V2
 
 	select ARCH_MXC_AUDMUX_V2
 
@@ -25,7 +24,6 @@ config SOC_IMX50
 
 config	SOC_IMX51
 
 config	SOC_IMX51
 
 	bool
 
 	bool
 
 	select CPU_V7
 
 	select CPU_V7
 
-	select ARM_L1_CACHE_SHIFT_6
 
 	select MXC_TZIC
 
 	select MXC_TZIC
 
 	select ARCH_MXC_IOMUX_V3
 
 	select ARCH_MXC_IOMUX_V3
 
 	select ARCH_MXC_AUDMUX_V2
 
 	select ARCH_MXC_AUDMUX_V2
 
@@ -35,7 +33,6 @@ config	SOC_IMX51
 
 config	SOC_IMX53
 
 config	SOC_IMX53
 
 	bool
 
 	bool
 
 	select CPU_V7
 
 	select CPU_V7
 
-	select ARM_L1_CACHE_SHIFT_6
 
 	select MXC_TZIC
 
 	select MXC_TZIC
 
 	select ARCH_MXC_IOMUX_V3
 
 	select ARCH_MXC_IOMUX_V3
 
 	select ARCH_MX53
 
 	select ARCH_MX53

+ 0 - 1
arch/arm/mach-omap2/Kconfig
Целия файл 

@@ -33,7 +33,6 @@ config ARCH_OMAP3
 
 	default y
 
 	default y
 
 	select CPU_V7
 
 	select CPU_V7
 
 	select USB_ARCH_HAS_EHCI
 
 	select USB_ARCH_HAS_EHCI
 
-	select ARM_L1_CACHE_SHIFT_6 if !ARCH_OMAP4
 
 	select ARCH_HAS_OPP
 
 	select ARCH_HAS_OPP
 
 	select PM_OPP if PM
 
 	select PM_OPP if PM
 
 	select ARM_CPU_SUSPEND if PM
 
 	select ARM_CPU_SUSPEND if PM

+ 1 - 0
arch/arm/mm/Kconfig
Целия файл 

@@ -882,6 +882,7 @@ config CACHE_XSC3L2
 
 
 
 config ARM_L1_CACHE_SHIFT_6
 
 config ARM_L1_CACHE_SHIFT_6
 
 	bool
 
 	bool
 
+	default y if CPU_V7
 
 	help
 
 	help
 
 	  Setting ARM L1 cache line size to 64 Bytes.
 
 	  Setting ARM L1 cache line size to 64 Bytes.