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@@ -16,13 +16,16 @@
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#include <linux/module.h>
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#include <linux/string.h>
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#include <linux/io.h>
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+#include <linux/spinlock.h>
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+
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+#include <mach/hardware.h>
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#include <asm/clkdev.h>
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#include <asm/div64.h>
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-#include <mach/hardware.h>
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struct clk {
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+ struct clk *parent;
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unsigned long rate;
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int users;
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int sw_locked;
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@@ -39,40 +42,60 @@ static unsigned long get_uart_rate(struct clk *clk);
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static int set_keytchclk_rate(struct clk *clk, unsigned long rate);
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static int set_div_rate(struct clk *clk, unsigned long rate);
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+
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+static struct clk clk_xtali = {
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+ .rate = EP93XX_EXT_CLK_RATE,
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+};
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static struct clk clk_uart1 = {
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+ .parent = &clk_xtali,
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.sw_locked = 1,
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.enable_reg = EP93XX_SYSCON_DEVCFG,
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.enable_mask = EP93XX_SYSCON_DEVCFG_U1EN,
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.get_rate = get_uart_rate,
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};
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static struct clk clk_uart2 = {
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+ .parent = &clk_xtali,
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.sw_locked = 1,
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.enable_reg = EP93XX_SYSCON_DEVCFG,
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.enable_mask = EP93XX_SYSCON_DEVCFG_U2EN,
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.get_rate = get_uart_rate,
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};
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static struct clk clk_uart3 = {
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+ .parent = &clk_xtali,
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.sw_locked = 1,
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.enable_reg = EP93XX_SYSCON_DEVCFG,
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.enable_mask = EP93XX_SYSCON_DEVCFG_U3EN,
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.get_rate = get_uart_rate,
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};
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-static struct clk clk_pll1;
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-static struct clk clk_f;
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-static struct clk clk_h;
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-static struct clk clk_p;
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-static struct clk clk_pll2;
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+static struct clk clk_pll1 = {
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+ .parent = &clk_xtali,
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+};
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+static struct clk clk_f = {
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+ .parent = &clk_pll1,
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+};
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+static struct clk clk_h = {
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+ .parent = &clk_pll1,
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+};
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+static struct clk clk_p = {
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+ .parent = &clk_pll1,
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+};
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+static struct clk clk_pll2 = {
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+ .parent = &clk_xtali,
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+};
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static struct clk clk_usb_host = {
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+ .parent = &clk_pll2,
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.enable_reg = EP93XX_SYSCON_PWRCNT,
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.enable_mask = EP93XX_SYSCON_PWRCNT_USH_EN,
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};
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static struct clk clk_keypad = {
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+ .parent = &clk_xtali,
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.sw_locked = 1,
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.enable_reg = EP93XX_SYSCON_KEYTCHCLKDIV,
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.enable_mask = EP93XX_SYSCON_KEYTCHCLKDIV_KEN,
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.set_rate = set_keytchclk_rate,
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};
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static struct clk clk_pwm = {
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+ .parent = &clk_xtali,
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.rate = EP93XX_EXT_CLK_RATE,
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};
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@@ -85,50 +108,62 @@ static struct clk clk_video = {
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/* DMA Clocks */
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static struct clk clk_m2p0 = {
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+ .parent = &clk_h,
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.enable_reg = EP93XX_SYSCON_PWRCNT,
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.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P0,
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};
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static struct clk clk_m2p1 = {
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+ .parent = &clk_h,
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.enable_reg = EP93XX_SYSCON_PWRCNT,
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.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P1,
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};
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static struct clk clk_m2p2 = {
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+ .parent = &clk_h,
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.enable_reg = EP93XX_SYSCON_PWRCNT,
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.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P2,
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};
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static struct clk clk_m2p3 = {
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+ .parent = &clk_h,
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.enable_reg = EP93XX_SYSCON_PWRCNT,
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.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P3,
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};
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static struct clk clk_m2p4 = {
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+ .parent = &clk_h,
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.enable_reg = EP93XX_SYSCON_PWRCNT,
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.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P4,
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};
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static struct clk clk_m2p5 = {
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+ .parent = &clk_h,
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.enable_reg = EP93XX_SYSCON_PWRCNT,
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.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P5,
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};
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static struct clk clk_m2p6 = {
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+ .parent = &clk_h,
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.enable_reg = EP93XX_SYSCON_PWRCNT,
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.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P6,
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};
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static struct clk clk_m2p7 = {
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+ .parent = &clk_h,
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.enable_reg = EP93XX_SYSCON_PWRCNT,
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.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P7,
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};
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static struct clk clk_m2p8 = {
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+ .parent = &clk_h,
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.enable_reg = EP93XX_SYSCON_PWRCNT,
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.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P8,
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};
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static struct clk clk_m2p9 = {
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+ .parent = &clk_h,
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.enable_reg = EP93XX_SYSCON_PWRCNT,
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.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P9,
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};
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static struct clk clk_m2m0 = {
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+ .parent = &clk_h,
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.enable_reg = EP93XX_SYSCON_PWRCNT,
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.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2M0,
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};
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static struct clk clk_m2m1 = {
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+ .parent = &clk_h,
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.enable_reg = EP93XX_SYSCON_PWRCNT,
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.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2M1,
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};
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@@ -137,6 +172,7 @@ static struct clk clk_m2m1 = {
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{ .dev_id = dev, .con_id = con, .clk = ck }
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static struct clk_lookup clocks[] = {
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+ INIT_CK(NULL, "xtali", &clk_xtali),
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INIT_CK("apb:uart1", NULL, &clk_uart1),
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INIT_CK("apb:uart2", NULL, &clk_uart2),
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INIT_CK("apb:uart3", NULL, &clk_uart3),
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@@ -163,48 +199,84 @@ static struct clk_lookup clocks[] = {
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INIT_CK(NULL, "m2m1", &clk_m2m1),
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};
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+static DEFINE_SPINLOCK(clk_lock);
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+
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+static void __clk_enable(struct clk *clk)
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+{
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+ if (!clk->users++) {
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+ if (clk->parent)
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+ __clk_enable(clk->parent);
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+
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+ if (clk->enable_reg) {
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+ u32 v;
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+
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+ v = __raw_readl(clk->enable_reg);
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+ v |= clk->enable_mask;
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+ if (clk->sw_locked)
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+ ep93xx_syscon_swlocked_write(v, clk->enable_reg);
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+ else
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+ __raw_writel(v, clk->enable_reg);
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+ }
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+ }
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+}
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int clk_enable(struct clk *clk)
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{
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- if (!clk->users++ && clk->enable_reg) {
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- u32 value;
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+ unsigned long flags;
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- value = __raw_readl(clk->enable_reg);
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- value |= clk->enable_mask;
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- if (clk->sw_locked)
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- ep93xx_syscon_swlocked_write(value, clk->enable_reg);
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- else
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- __raw_writel(value, clk->enable_reg);
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- }
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+ if (!clk)
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+ return -EINVAL;
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+
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+ spin_lock_irqsave(&clk_lock, flags);
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+ __clk_enable(clk);
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+ spin_unlock_irqrestore(&clk_lock, flags);
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return 0;
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}
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EXPORT_SYMBOL(clk_enable);
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-void clk_disable(struct clk *clk)
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+static void __clk_disable(struct clk *clk)
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{
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- if (!--clk->users && clk->enable_reg) {
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- u32 value;
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+ if (!--clk->users) {
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+ if (clk->enable_reg) {
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+ u32 v;
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+
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+ v = __raw_readl(clk->enable_reg);
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+ v &= ~clk->enable_mask;
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+ if (clk->sw_locked)
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+ ep93xx_syscon_swlocked_write(v, clk->enable_reg);
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+ else
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+ __raw_writel(v, clk->enable_reg);
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+ }
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- value = __raw_readl(clk->enable_reg);
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- value &= ~clk->enable_mask;
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- if (clk->sw_locked)
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- ep93xx_syscon_swlocked_write(value, clk->enable_reg);
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- else
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- __raw_writel(value, clk->enable_reg);
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+ if (clk->parent)
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+ __clk_disable(clk->parent);
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}
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}
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+
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+void clk_disable(struct clk *clk)
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+{
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+ unsigned long flags;
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+
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+ if (!clk)
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+ return;
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+
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+ spin_lock_irqsave(&clk_lock, flags);
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+ __clk_disable(clk);
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+ spin_unlock_irqrestore(&clk_lock, flags);
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+}
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EXPORT_SYMBOL(clk_disable);
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static unsigned long get_uart_rate(struct clk *clk)
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{
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+ unsigned long rate = clk_get_rate(clk->parent);
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u32 value;
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value = __raw_readl(EP93XX_SYSCON_PWRCNT);
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if (value & EP93XX_SYSCON_PWRCNT_UARTBAUD)
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- return EP93XX_EXT_CLK_RATE;
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+ return rate;
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else
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- return EP93XX_EXT_CLK_RATE / 2;
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+ return rate / 2;
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}
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unsigned long clk_get_rate(struct clk *clk)
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@@ -244,16 +316,16 @@ static int set_keytchclk_rate(struct clk *clk, unsigned long rate)
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return 0;
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}
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-static unsigned long calc_clk_div(unsigned long rate, int *psel, int *esel,
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- int *pdiv, int *div)
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+static int calc_clk_div(struct clk *clk, unsigned long rate,
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+ int *psel, int *esel, int *pdiv, int *div)
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{
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- unsigned long max_rate, best_rate = 0,
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- actual_rate = 0, mclk_rate = 0, rate_err = -1;
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+ struct clk *mclk;
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+ unsigned long max_rate, actual_rate, mclk_rate, rate_err = -1;
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int i, found = 0, __div = 0, __pdiv = 0;
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/* Don't exceed the maximum rate */
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max_rate = max(max(clk_pll1.rate / 4, clk_pll2.rate / 4),
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- (unsigned long)EP93XX_EXT_CLK_RATE / 4);
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+ clk_xtali.rate / 4);
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rate = min(rate, max_rate);
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/*
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@@ -267,11 +339,12 @@ static unsigned long calc_clk_div(unsigned long rate, int *psel, int *esel,
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*/
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for (i = 0; i < 3; i++) {
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if (i == 0)
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- mclk_rate = EP93XX_EXT_CLK_RATE * 2;
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+ mclk = &clk_xtali;
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else if (i == 1)
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- mclk_rate = clk_pll1.rate * 2;
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- else if (i == 2)
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- mclk_rate = clk_pll2.rate * 2;
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+ mclk = &clk_pll1;
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+ else
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+ mclk = &clk_pll2;
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+ mclk_rate = mclk->rate * 2;
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/* Try each predivider value */
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for (__pdiv = 4; __pdiv <= 6; __pdiv++) {
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@@ -286,7 +359,8 @@ static unsigned long calc_clk_div(unsigned long rate, int *psel, int *esel,
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*div = __div;
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*psel = (i == 2);
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*esel = (i != 0);
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- best_rate = actual_rate;
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+ clk->parent = mclk;
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+ clk->rate = actual_rate;
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rate_err = abs(actual_rate - rate);
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found = 1;
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}
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@@ -294,21 +368,19 @@ static unsigned long calc_clk_div(unsigned long rate, int *psel, int *esel,
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}
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if (!found)
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- return 0;
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+ return -EINVAL;
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- return best_rate;
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+ return 0;
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}
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static int set_div_rate(struct clk *clk, unsigned long rate)
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{
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- unsigned long actual_rate;
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- int psel = 0, esel = 0, pdiv = 0, div = 0;
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+ int err, psel = 0, esel = 0, pdiv = 0, div = 0;
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u32 val;
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- actual_rate = calc_clk_div(rate, &psel, &esel, &pdiv, &div);
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- if (actual_rate == 0)
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- return -EINVAL;
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- clk->rate = actual_rate;
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+ err = calc_clk_div(clk, rate, &psel, &esel, &pdiv, &div);
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+ if (err)
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+ return err;
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/* Clear the esel, psel, pdiv and div bits */
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val = __raw_readl(clk->enable_reg);
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@@ -344,7 +416,7 @@ static unsigned long calc_pll_rate(u32 config_word)
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unsigned long long rate;
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int i;
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- rate = EP93XX_EXT_CLK_RATE;
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+ rate = clk_xtali.rate;
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rate *= ((config_word >> 11) & 0x1f) + 1; /* X1FBD */
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rate *= ((config_word >> 5) & 0x3f) + 1; /* X2FBD */
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do_div(rate, (config_word & 0x1f) + 1); /* X2IPD */
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@@ -377,7 +449,7 @@ static int __init ep93xx_clock_init(void)
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value = __raw_readl(EP93XX_SYSCON_CLOCK_SET1);
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if (!(value & 0x00800000)) { /* PLL1 bypassed? */
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- clk_pll1.rate = EP93XX_EXT_CLK_RATE;
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+ clk_pll1.rate = clk_xtali.rate;
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} else {
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clk_pll1.rate = calc_pll_rate(value);
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}
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@@ -388,7 +460,7 @@ static int __init ep93xx_clock_init(void)
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value = __raw_readl(EP93XX_SYSCON_CLOCK_SET2);
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if (!(value & 0x00080000)) { /* PLL2 bypassed? */
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- clk_pll2.rate = EP93XX_EXT_CLK_RATE;
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+ clk_pll2.rate = clk_xtali.rate;
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} else if (value & 0x00040000) { /* PLL2 enabled? */
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clk_pll2.rate = calc_pll_rate(value);
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} else {
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