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@@ -323,6 +323,21 @@ static struct clk z_clk = {
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.ops = &zclk_ops,
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};
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+/*
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+ * It seems only 1/2 divider is usable in manual mode. 1/2 / 2/3
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+ * switching is only available in auto-DVFS mode
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+ */
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+SH_FIXED_RATIO_CLK(pll0_div2_clk, pll0_clk, div2);
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+
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+static struct clk z2_clk = {
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+ .parent = &pll0_div2_clk,
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+ .div_mask = 0x1f,
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+ .enable_bit = 0,
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+ /* We'll need to access FRQCRB and FRQCRC */
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+ .enable_reg = (void __iomem *)FRQCRB,
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+ .ops = &zclk_ops,
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+};
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+
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static struct clk *main_clks[] = {
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&extalr_clk,
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&extal1_clk,
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@@ -341,6 +356,8 @@ static struct clk *main_clks[] = {
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&pll2s_clk,
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&pll2h_clk,
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&z_clk,
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+ &pll0_div2_clk,
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+ &z2_clk,
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};
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/* DIV4 */
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