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@@ -36,6 +36,7 @@ struct dice {
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struct mutex mutex;
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unsigned int global_offset;
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unsigned int rx_offset;
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+ unsigned int clock_caps;
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struct fw_address_handler notification_handler;
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int owner_generation;
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int dev_lock_count; /* > 0 driver, < 0 userspace */
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@@ -830,9 +831,10 @@ static int dice_interface_check(struct fw_unit *unit)
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return 0;
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}
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-static int dice_init_offsets(struct dice *dice)
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+static int dice_read_params(struct dice *dice)
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{
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__be32 pointers[6];
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+ __be32 value;
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int err;
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err = snd_fw_transaction(dice->unit, TCODE_READ_BLOCK_REQUEST,
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@@ -844,6 +846,23 @@ static int dice_init_offsets(struct dice *dice)
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dice->global_offset = be32_to_cpu(pointers[0]) * 4;
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dice->rx_offset = be32_to_cpu(pointers[4]) * 4;
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+ /* some very old firmwares don't tell about their clock support */
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+ if (be32_to_cpu(pointers[1]) * 4 >= GLOBAL_CLOCK_CAPABILITIES + 4) {
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+ err = snd_fw_transaction(
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+ dice->unit, TCODE_READ_QUADLET_REQUEST,
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+ global_address(dice, GLOBAL_CLOCK_CAPABILITIES),
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+ &value, 4, 0);
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+ if (err < 0)
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+ return err;
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+ dice->clock_caps = be32_to_cpu(value);
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+ } else {
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+ /* this should be supported by any device */
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+ dice->clock_caps = CLOCK_CAP_RATE_44100 |
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+ CLOCK_CAP_RATE_48000 |
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+ CLOCK_CAP_SOURCE_ARX1 |
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+ CLOCK_CAP_SOURCE_INTERNAL;
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+ }
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+
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return 0;
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}
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@@ -905,7 +924,7 @@ static int dice_probe(struct fw_unit *unit, const struct ieee1394_device_id *id)
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dice->unit = unit;
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init_waitqueue_head(&dice->hwdep_wait);
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- err = dice_init_offsets(dice);
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+ err = dice_read_params(dice);
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if (err < 0)
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goto err_mutex;
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