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@@ -108,6 +108,8 @@
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#define GPMC_HAS_WR_ACCESS 0x1
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#define GPMC_HAS_WR_DATA_MUX_BUS 0x2
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+#define GPMC_NR_WAITPINS 4
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+
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/* XXX: Only NAND irq has been considered,currently these are the only ones used
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*/
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#define GPMC_NR_IRQ 2
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@@ -153,6 +155,7 @@ static struct resource gpmc_cs_mem[GPMC_CS_NUM];
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static DEFINE_SPINLOCK(gpmc_mem_lock);
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/* Define chip-selects as reserved by default until probe completes */
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static unsigned int gpmc_cs_map = ((1 << GPMC_CS_NUM) - 1);
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+static unsigned int gpmc_nr_waitpins;
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static struct device *gpmc_dev;
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static int gpmc_irq;
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static resource_size_t phys_base, mem_size;
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@@ -1294,6 +1297,13 @@ static int gpmc_probe_dt(struct platform_device *pdev)
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if (!of_id)
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return 0;
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+ ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins",
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+ &gpmc_nr_waitpins);
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+ if (ret < 0) {
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+ pr_err("%s: number of wait pins not found!\n", __func__);
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+ return ret;
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+ }
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+
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for_each_node_by_name(child, "nand") {
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ret = gpmc_probe_nand_child(pdev, child);
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if (ret < 0) {
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@@ -1372,6 +1382,9 @@ static int gpmc_probe(struct platform_device *pdev)
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/* Now the GPMC is initialised, unreserve the chip-selects */
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gpmc_cs_map = 0;
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+ if (!pdev->dev.of_node)
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+ gpmc_nr_waitpins = GPMC_NR_WAITPINS;
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+
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rc = gpmc_probe_dt(pdev);
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if (rc < 0) {
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clk_disable_unprepare(gpmc_l3_clk);
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