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@@ -1892,6 +1892,15 @@ static void handle_ep0_ctrl_req(struct pxa_udc *udc,
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nuke(ep, -EPROTO);
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+ /*
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+ * In the PXA320 manual, in the section about Back-to-Back setup
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+ * packets, it describes this situation. The solution is to set OPC to
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+ * get rid of the status packet, and then continue with the setup
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+ * packet. Generalize to pxa27x CPUs.
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+ */
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+ if (epout_has_pkt(ep) && (ep_count_bytes_remain(ep) == 0))
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+ udc_ep_writel(ep, UDCCSR, UDCCSR0_OPC);
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+
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/* read SETUP packet */
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for (i = 0; i < 2; i++) {
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if (unlikely(ep_is_empty(ep)))
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@@ -1965,6 +1974,8 @@ stall:
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* cleared by software.
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* - clearing UDCCSR0_OPC always flushes ep0. If in setup stage, never do it
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* before reading ep0.
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+ * This is true only for PXA27x. This is not true anymore for PXA3xx family
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+ * (check Back-to-Back setup packet in developers guide).
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* - irq can be called on a "packet complete" event (opc_irq=1), while
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* UDCCSR0_OPC is not yet raised (delta can be as big as 100ms
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* from experimentation).
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@@ -2575,7 +2586,7 @@ static struct platform_driver udc_driver = {
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static int __init udc_init(void)
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{
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- if (!cpu_is_pxa27x())
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+ if (!cpu_is_pxa27x() && !cpu_is_pxa3xx())
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return -ENODEV;
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printk(KERN_INFO "%s: version %s\n", driver_name, DRIVER_VERSION);
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