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@@ -266,10 +266,21 @@
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#define MV643XX_ETH_IPG_INT_RX(value) ((value & 0x3fff) << 8)
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+#if defined(__BIG_ENDIAN)
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#define MV643XX_ETH_PORT_SDMA_CONFIG_DEFAULT_VALUE \
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MV643XX_ETH_RX_BURST_SIZE_4_64BIT | \
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MV643XX_ETH_IPG_INT_RX(0) | \
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MV643XX_ETH_TX_BURST_SIZE_4_64BIT
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+#elif defined(__LITTLE_ENDIAN)
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+#define MV643XX_ETH_PORT_SDMA_CONFIG_DEFAULT_VALUE \
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+ MV643XX_ETH_RX_BURST_SIZE_4_64BIT | \
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+ MV643XX_ETH_BLM_RX_NO_SWAP | \
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+ MV643XX_ETH_BLM_TX_NO_SWAP | \
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+ MV643XX_ETH_IPG_INT_RX(0) | \
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+ MV643XX_ETH_TX_BURST_SIZE_4_64BIT
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+#else
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+#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
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+#endif
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/* These macros describe Ethernet Port serial control reg (PSCR) bits */
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#define MV643XX_ETH_SERIAL_PORT_DISABLE 0
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