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@@ -121,6 +121,8 @@
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/* Descriptor table word 0 bit (when DTA32M = 1) */
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#define SATA_RCAR_DTEND BIT(0)
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+#define SATA_RCAR_DMA_BOUNDARY 0x1FFFFFFEUL
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+
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struct sata_rcar_priv {
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void __iomem *base;
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struct clk *clk;
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@@ -128,41 +130,44 @@ struct sata_rcar_priv {
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static void sata_rcar_phy_initialize(struct sata_rcar_priv *priv)
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{
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+ void __iomem *base = priv->base;
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+
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/* idle state */
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- iowrite32(0, priv->base + SATAPHYADDR_REG);
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+ iowrite32(0, base + SATAPHYADDR_REG);
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/* reset */
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- iowrite32(SATAPHYRESET_PHYRST, priv->base + SATAPHYRESET_REG);
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+ iowrite32(SATAPHYRESET_PHYRST, base + SATAPHYRESET_REG);
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udelay(10);
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/* deassert reset */
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- iowrite32(0, priv->base + SATAPHYRESET_REG);
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+ iowrite32(0, base + SATAPHYRESET_REG);
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}
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static void sata_rcar_phy_write(struct sata_rcar_priv *priv, u16 reg, u32 val,
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int group)
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{
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+ void __iomem *base = priv->base;
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int timeout;
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/* deassert reset */
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- iowrite32(0, priv->base + SATAPHYRESET_REG);
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+ iowrite32(0, base + SATAPHYRESET_REG);
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/* lane 1 */
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- iowrite32(SATAPHYACCEN_PHYLANE, priv->base + SATAPHYACCEN_REG);
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+ iowrite32(SATAPHYACCEN_PHYLANE, base + SATAPHYACCEN_REG);
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/* write phy register value */
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- iowrite32(val, priv->base + SATAPHYWDATA_REG);
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+ iowrite32(val, base + SATAPHYWDATA_REG);
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/* set register group */
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if (group)
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reg |= SATAPHYADDR_PHYRATEMODE;
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/* write command */
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- iowrite32(SATAPHYADDR_PHYCMD_WRITE | reg, priv->base + SATAPHYADDR_REG);
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+ iowrite32(SATAPHYADDR_PHYCMD_WRITE | reg, base + SATAPHYADDR_REG);
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/* wait for ack */
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for (timeout = 0; timeout < 100; timeout++) {
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- val = ioread32(priv->base + SATAPHYACK_REG);
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+ val = ioread32(base + SATAPHYACK_REG);
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if (val & SATAPHYACK_PHYACK)
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break;
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}
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if (timeout >= 100)
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pr_err("%s timeout\n", __func__);
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/* idle state */
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- iowrite32(0, priv->base + SATAPHYADDR_REG);
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+ iowrite32(0, base + SATAPHYADDR_REG);
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}
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static void sata_rcar_freeze(struct ata_port *ap)
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@@ -178,14 +183,15 @@ static void sata_rcar_freeze(struct ata_port *ap)
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static void sata_rcar_thaw(struct ata_port *ap)
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{
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struct sata_rcar_priv *priv = ap->host->private_data;
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+ void __iomem *base = priv->base;
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/* ack */
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- iowrite32(~SATA_RCAR_INT_MASK, priv->base + SATAINTSTAT_REG);
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+ iowrite32(~(u32)SATA_RCAR_INT_MASK, base + SATAINTSTAT_REG);
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ata_sff_thaw(ap);
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/* unmask */
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- iowrite32(0x7ff & ~SATA_RCAR_INT_MASK, priv->base + SATAINTMASK_REG);
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+ iowrite32(0x7ff & ~SATA_RCAR_INT_MASK, base + SATAINTMASK_REG);
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}
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static void sata_rcar_ioread16_rep(void __iomem *reg, void *buffer, int count)
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@@ -474,11 +480,10 @@ static void sata_rcar_bmdma_fill_sg(struct ata_queued_cmd *qc)
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struct ata_port *ap = qc->ap;
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struct ata_bmdma_prd *prd = ap->bmdma_prd;
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struct scatterlist *sg;
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- unsigned int si, pi;
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+ unsigned int si;
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- pi = 0;
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for_each_sg(qc->sg, sg, qc->n_elem, si) {
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- u32 addr, sg_len, len;
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+ u32 addr, sg_len;
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/*
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* Note: h/w doesn't support 64-bit, so we unconditionally
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@@ -487,24 +492,13 @@ static void sata_rcar_bmdma_fill_sg(struct ata_queued_cmd *qc)
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addr = (u32)sg_dma_address(sg);
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sg_len = sg_dma_len(sg);
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- /* H/w transfer count is only 29 bits long, let's be careful */
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- while (sg_len) {
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- len = sg_len;
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- if (len > 0x1ffffffe)
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- len = 0x1ffffffe;
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-
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- prd[pi].addr = cpu_to_le32(addr);
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- prd[pi].flags_len = cpu_to_le32(len);
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- VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len);
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-
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- pi++;
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- sg_len -= len;
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- addr += len;
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- }
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+ prd[si].addr = cpu_to_le32(addr);
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+ prd[si].flags_len = cpu_to_le32(sg_len);
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+ VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", si, addr, sg_len);
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}
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/* end-of-table flag */
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- prd[pi - 1].addr |= cpu_to_le32(SATA_RCAR_DTEND);
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+ prd[si - 1].addr |= cpu_to_le32(SATA_RCAR_DTEND);
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}
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static void sata_rcar_qc_prep(struct ata_queued_cmd *qc)
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@@ -519,15 +513,16 @@ static void sata_rcar_bmdma_setup(struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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unsigned int rw = qc->tf.flags & ATA_TFLAG_WRITE;
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- u32 dmactl;
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struct sata_rcar_priv *priv = ap->host->private_data;
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+ void __iomem *base = priv->base;
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+ u32 dmactl;
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/* load PRD table addr. */
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mb(); /* make sure PRD table writes are visible to controller */
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- iowrite32(ap->bmdma_prd_dma, priv->base + ATAPI_DTB_ADR_REG);
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+ iowrite32(ap->bmdma_prd_dma, base + ATAPI_DTB_ADR_REG);
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/* specify data direction, triple-check start bit is clear */
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- dmactl = ioread32(priv->base + ATAPI_CONTROL1_REG);
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+ dmactl = ioread32(base + ATAPI_CONTROL1_REG);
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dmactl &= ~(ATAPI_CONTROL1_RW | ATAPI_CONTROL1_STOP);
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if (dmactl & ATAPI_CONTROL1_START) {
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dmactl &= ~ATAPI_CONTROL1_START;
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@@ -535,7 +530,7 @@ static void sata_rcar_bmdma_setup(struct ata_queued_cmd *qc)
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}
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if (!rw)
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dmactl |= ATAPI_CONTROL1_RW;
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- iowrite32(dmactl, priv->base + ATAPI_CONTROL1_REG);
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+ iowrite32(dmactl, base + ATAPI_CONTROL1_REG);
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/* issue r/w command */
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ap->ops->sff_exec_command(ap, &qc->tf);
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@@ -544,28 +539,30 @@ static void sata_rcar_bmdma_setup(struct ata_queued_cmd *qc)
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static void sata_rcar_bmdma_start(struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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- u32 dmactl;
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struct sata_rcar_priv *priv = ap->host->private_data;
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+ void __iomem *base = priv->base;
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+ u32 dmactl;
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/* start host DMA transaction */
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- dmactl = ioread32(priv->base + ATAPI_CONTROL1_REG);
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+ dmactl = ioread32(base + ATAPI_CONTROL1_REG);
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dmactl &= ~ATAPI_CONTROL1_STOP;
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dmactl |= ATAPI_CONTROL1_START;
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- iowrite32(dmactl, priv->base + ATAPI_CONTROL1_REG);
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+ iowrite32(dmactl, base + ATAPI_CONTROL1_REG);
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}
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static void sata_rcar_bmdma_stop(struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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struct sata_rcar_priv *priv = ap->host->private_data;
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+ void __iomem *base = priv->base;
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u32 dmactl;
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/* force termination of DMA transfer if active */
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- dmactl = ioread32(priv->base + ATAPI_CONTROL1_REG);
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+ dmactl = ioread32(base + ATAPI_CONTROL1_REG);
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if (dmactl & ATAPI_CONTROL1_START) {
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dmactl &= ~ATAPI_CONTROL1_START;
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dmactl |= ATAPI_CONTROL1_STOP;
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- iowrite32(dmactl, priv->base + ATAPI_CONTROL1_REG);
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+ iowrite32(dmactl, base + ATAPI_CONTROL1_REG);
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}
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/* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
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@@ -575,8 +572,8 @@ static void sata_rcar_bmdma_stop(struct ata_queued_cmd *qc)
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static u8 sata_rcar_bmdma_status(struct ata_port *ap)
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{
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struct sata_rcar_priv *priv = ap->host->private_data;
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- u32 status;
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u8 host_stat = 0;
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+ u32 status;
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status = ioread32(priv->base + ATAPI_STATUS_REG);
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if (status & ATAPI_STATUS_DEVINT)
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@@ -588,7 +585,14 @@ static u8 sata_rcar_bmdma_status(struct ata_port *ap)
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}
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static struct scsi_host_template sata_rcar_sht = {
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- ATA_BMDMA_SHT(DRV_NAME),
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+ ATA_BASE_SHT(DRV_NAME),
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+ /*
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+ * This controller allows transfer chunks up to 512MB which cross 64KB
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+ * boundaries, therefore the DMA limits are more relaxed than standard
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+ * ATA SFF.
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+ */
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+ .sg_tablesize = ATA_MAX_PRD,
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+ .dma_boundary = SATA_RCAR_DMA_BOUNDARY,
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};
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static struct ata_port_operations sata_rcar_port_ops = {
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@@ -668,19 +672,20 @@ static irqreturn_t sata_rcar_interrupt(int irq, void *dev_instance)
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{
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struct ata_host *host = dev_instance;
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struct sata_rcar_priv *priv = host->private_data;
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- struct ata_port *ap;
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+ void __iomem *base = priv->base;
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unsigned int handled = 0;
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+ struct ata_port *ap;
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u32 sataintstat;
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unsigned long flags;
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spin_lock_irqsave(&host->lock, flags);
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- sataintstat = ioread32(priv->base + SATAINTSTAT_REG);
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+ sataintstat = ioread32(base + SATAINTSTAT_REG);
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sataintstat &= SATA_RCAR_INT_MASK;
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if (!sataintstat)
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goto done;
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/* ack */
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- iowrite32(~sataintstat & 0x7ff, priv->base + SATAINTSTAT_REG);
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+ iowrite32(~sataintstat & 0x7ff, base + SATAINTSTAT_REG);
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ap = host->ports[0];
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@@ -702,15 +707,16 @@ static void sata_rcar_setup_port(struct ata_host *host)
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struct ata_port *ap = host->ports[0];
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struct ata_ioports *ioaddr = &ap->ioaddr;
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struct sata_rcar_priv *priv = host->private_data;
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+ void __iomem *base = priv->base;
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ap->ops = &sata_rcar_port_ops;
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ap->pio_mask = ATA_PIO4;
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ap->udma_mask = ATA_UDMA6;
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ap->flags |= ATA_FLAG_SATA;
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- ioaddr->cmd_addr = priv->base + SDATA_REG;
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- ioaddr->ctl_addr = priv->base + SSDEVCON_REG;
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- ioaddr->scr_addr = priv->base + SCRSSTS_REG;
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+ ioaddr->cmd_addr = base + SDATA_REG;
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+ ioaddr->ctl_addr = base + SSDEVCON_REG;
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+ ioaddr->scr_addr = base + SCRSSTS_REG;
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ioaddr->altstatus_addr = ioaddr->ctl_addr;
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ioaddr->data_addr = ioaddr->cmd_addr + (ATA_REG_DATA << 2);
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@@ -728,6 +734,7 @@ static void sata_rcar_setup_port(struct ata_host *host)
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static void sata_rcar_init_controller(struct ata_host *host)
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{
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struct sata_rcar_priv *priv = host->private_data;
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+ void __iomem *base = priv->base;
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u32 val;
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/* reset and setup phy */
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@@ -740,27 +747,27 @@ static void sata_rcar_init_controller(struct ata_host *host)
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sata_rcar_phy_write(priv, SATAPCTLR4_REG, 0x28E80000, 0);
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/* SATA-IP reset state */
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- val = ioread32(priv->base + ATAPI_CONTROL1_REG);
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+ val = ioread32(base + ATAPI_CONTROL1_REG);
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val |= ATAPI_CONTROL1_RESET;
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- iowrite32(val, priv->base + ATAPI_CONTROL1_REG);
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+ iowrite32(val, base + ATAPI_CONTROL1_REG);
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/* ISM mode, PRD mode, DTEND flag at bit 0 */
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- val = ioread32(priv->base + ATAPI_CONTROL1_REG);
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+ val = ioread32(base + ATAPI_CONTROL1_REG);
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val |= ATAPI_CONTROL1_ISM;
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val |= ATAPI_CONTROL1_DESE;
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val |= ATAPI_CONTROL1_DTA32M;
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- iowrite32(val, priv->base + ATAPI_CONTROL1_REG);
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+ iowrite32(val, base + ATAPI_CONTROL1_REG);
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/* Release the SATA-IP from the reset state */
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- val = ioread32(priv->base + ATAPI_CONTROL1_REG);
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+ val = ioread32(base + ATAPI_CONTROL1_REG);
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val &= ~ATAPI_CONTROL1_RESET;
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- iowrite32(val, priv->base + ATAPI_CONTROL1_REG);
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+ iowrite32(val, base + ATAPI_CONTROL1_REG);
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/* ack and mask */
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- iowrite32(0, priv->base + SATAINTSTAT_REG);
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- iowrite32(0x7ff, priv->base + SATAINTMASK_REG);
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+ iowrite32(0, base + SATAINTSTAT_REG);
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+ iowrite32(0x7ff, base + SATAINTMASK_REG);
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/* enable interrupts */
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- iowrite32(ATAPI_INT_ENABLE_SATAINT, priv->base + ATAPI_INT_ENABLE_REG);
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+ iowrite32(ATAPI_INT_ENABLE_SATAINT, base + ATAPI_INT_ENABLE_REG);
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}
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static int sata_rcar_probe(struct platform_device *pdev)
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@@ -825,16 +832,17 @@ cleanup:
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static int sata_rcar_remove(struct platform_device *pdev)
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{
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- struct ata_host *host = dev_get_drvdata(&pdev->dev);
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+ struct ata_host *host = platform_get_drvdata(pdev);
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struct sata_rcar_priv *priv = host->private_data;
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+ void __iomem *base = priv->base;
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ata_host_detach(host);
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/* disable interrupts */
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- iowrite32(0, priv->base + ATAPI_INT_ENABLE_REG);
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+ iowrite32(0, base + ATAPI_INT_ENABLE_REG);
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/* ack and mask */
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- iowrite32(0, priv->base + SATAINTSTAT_REG);
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- iowrite32(0x7ff, priv->base + SATAINTMASK_REG);
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+ iowrite32(0, base + SATAINTSTAT_REG);
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+ iowrite32(0x7ff, base + SATAINTMASK_REG);
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clk_disable(priv->clk);
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@@ -846,14 +854,15 @@ static int sata_rcar_suspend(struct device *dev)
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{
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struct ata_host *host = dev_get_drvdata(dev);
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struct sata_rcar_priv *priv = host->private_data;
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+ void __iomem *base = priv->base;
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int ret;
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ret = ata_host_suspend(host, PMSG_SUSPEND);
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if (!ret) {
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/* disable interrupts */
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- iowrite32(0, priv->base + ATAPI_INT_ENABLE_REG);
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+ iowrite32(0, base + ATAPI_INT_ENABLE_REG);
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/* mask */
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- iowrite32(0x7ff, priv->base + SATAINTMASK_REG);
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+ iowrite32(0x7ff, base + SATAINTMASK_REG);
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clk_disable(priv->clk);
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}
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@@ -865,14 +874,15 @@ static int sata_rcar_resume(struct device *dev)
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{
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struct ata_host *host = dev_get_drvdata(dev);
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struct sata_rcar_priv *priv = host->private_data;
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+ void __iomem *base = priv->base;
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clk_enable(priv->clk);
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/* ack and mask */
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- iowrite32(0, priv->base + SATAINTSTAT_REG);
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- iowrite32(0x7ff, priv->base + SATAINTMASK_REG);
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+ iowrite32(0, base + SATAINTSTAT_REG);
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+ iowrite32(0x7ff, base + SATAINTMASK_REG);
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/* enable interrupts */
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- iowrite32(ATAPI_INT_ENABLE_SATAINT, priv->base + ATAPI_INT_ENABLE_REG);
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+ iowrite32(ATAPI_INT_ENABLE_SATAINT, base + ATAPI_INT_ENABLE_REG);
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|
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|
ata_host_resume(host);
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|