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@@ -387,6 +387,35 @@ DEFINE_CLOCK(csi_clk, 0, CCM_CGR3, 0, get_rate_csi, NULL);
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DEFINE_CLOCK(iim_clk, 0, CCM_CGR3, 2, NULL, NULL);
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DEFINE_CLOCK(gpu2d_clk, 0, CCM_CGR3, 4, NULL, NULL);
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+static int clk_dummy_enable(struct clk *clk)
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+{
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+ return 0;
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+}
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+
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+static void clk_dummy_disable(struct clk *clk)
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+{
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+}
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+
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+static unsigned long get_rate_nfc(struct clk *clk)
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+{
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+ unsigned long div1;
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+
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+ div1 = (__raw_readl(CCM_BASE + CCM_PDR4) >> 28) + 1;
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+
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+ return get_rate_ahb(NULL) / div1;
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+}
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+
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+/* NAND Controller: It seems it can't be disabled */
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+static struct clk nfc_clk = {
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+ .id = 0,
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+ .enable_reg = 0,
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+ .enable_shift = 0,
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+ .get_rate = get_rate_nfc,
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+ .set_rate = NULL, /* set_rate_nfc, */
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+ .enable = clk_dummy_enable,
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+ .disable = clk_dummy_disable
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+};
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+
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#define _REGISTER_CLOCK(d, n, c) \
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{ \
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.dev_id = d, \
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@@ -449,6 +478,7 @@ static struct clk_lookup lookups[] = {
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_REGISTER_CLOCK(NULL, "csi", csi_clk)
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_REGISTER_CLOCK(NULL, "iim", iim_clk)
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_REGISTER_CLOCK(NULL, "gpu2d", gpu2d_clk)
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+ _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
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};
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int __init mx35_clocks_init()
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