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@@ -1123,8 +1123,9 @@ static int iommu_setup_msi(struct amd_iommu *iommu)
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{
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int r;
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- if (pci_enable_msi(iommu->dev))
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- return 1;
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+ r = pci_enable_msi(iommu->dev);
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+ if (r)
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+ return r;
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r = request_threaded_irq(iommu->dev->irq,
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amd_iommu_int_handler,
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@@ -1134,27 +1135,36 @@ static int iommu_setup_msi(struct amd_iommu *iommu)
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if (r) {
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pci_disable_msi(iommu->dev);
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- return 1;
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+ return r;
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}
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iommu->int_enabled = true;
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- iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
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-
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- if (iommu->ppr_log != NULL)
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- iommu_feature_enable(iommu, CONTROL_PPFINT_EN);
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return 0;
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}
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static int iommu_init_msi(struct amd_iommu *iommu)
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{
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+ int ret;
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+
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if (iommu->int_enabled)
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- return 0;
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+ goto enable_faults;
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if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSI))
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- return iommu_setup_msi(iommu);
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+ ret = iommu_setup_msi(iommu);
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+ else
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+ ret = -ENODEV;
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- return 1;
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+ if (ret)
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+ return ret;
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+
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+enable_faults:
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+ iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
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+
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+ if (iommu->ppr_log != NULL)
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+ iommu_feature_enable(iommu, CONTROL_PPFINT_EN);
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+
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+ return 0;
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}
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/****************************************************************************
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