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@@ -1404,3 +1404,37 @@ void ar9003_mci_bt_gain_ctrl(struct ath_hw *ah)
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/* Force another 2g5g update at next scanning */
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mci->update_2g5g = true;
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}
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+
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+void ar9003_mci_set_power_awake(struct ath_hw *ah)
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+{
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+ u32 btcoex_ctrl2, diag_sw;
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+ int i;
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+ u8 lna_ctrl, bt_sleep;
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+
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+ for (i = 0; i < AH_WAIT_TIMEOUT; i++) {
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+ btcoex_ctrl2 = REG_READ(ah, AR_BTCOEX_CTRL2);
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+ if (btcoex_ctrl2 != 0xdeadbeef)
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+ break;
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+ udelay(AH_TIME_QUANTUM);
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+ }
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+ REG_WRITE(ah, AR_BTCOEX_CTRL2, (btcoex_ctrl2 | BIT(23)));
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+
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+ for (i = 0; i < AH_WAIT_TIMEOUT; i++) {
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+ diag_sw = REG_READ(ah, AR_DIAG_SW);
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+ if (diag_sw != 0xdeadbeef)
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+ break;
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+ udelay(AH_TIME_QUANTUM);
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+ }
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+ REG_WRITE(ah, AR_DIAG_SW, (diag_sw | BIT(27) | BIT(19) | BIT(18)));
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+ lna_ctrl = REG_READ(ah, AR_OBS_BUS_CTRL) & 0x3;
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+ bt_sleep = REG_READ(ah, AR_MCI_RX_STATUS) & AR_MCI_RX_REMOTE_SLEEP;
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+
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+ REG_WRITE(ah, AR_BTCOEX_CTRL2, btcoex_ctrl2);
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+ REG_WRITE(ah, AR_DIAG_SW, diag_sw);
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+
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+ if (bt_sleep && (lna_ctrl == 2)) {
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+ REG_SET_BIT(ah, AR_BTCOEX_RC, 0x1);
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+ REG_CLR_BIT(ah, AR_BTCOEX_RC, 0x1);
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+ udelay(50);
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+ }
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+}
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