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@@ -916,6 +916,11 @@ static void assert_pch_pll(struct drm_i915_private *dev_priv,
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u32 val;
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bool cur_state;
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+ if (HAS_PCH_LPT(dev_priv->dev)) {
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+ DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
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+ return;
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+ }
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+
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if (!intel_crtc->pch_pll) {
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WARN(1, "asserting PCH PLL enabled with no PLL\n");
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return;
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@@ -1101,6 +1106,11 @@ static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
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u32 val;
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bool enabled;
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+ if (HAS_PCH_LPT(dev_priv->dev)) {
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+ DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
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+ return;
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+ }
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+
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val = I915_READ(PCH_DREF_CONTROL);
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enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
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DREF_SUPERSPREAD_SOURCE_MASK));
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@@ -4406,8 +4416,12 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
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DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
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drm_mode_debug_printmodeline(mode);
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- /* CPU eDP is the only output that doesn't need a PCH PLL of its own */
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- if (!is_cpu_edp) {
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+ /* CPU eDP is the only output that doesn't need a PCH PLL of its own on
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+ * pre-Haswell/LPT generation */
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+ if (HAS_PCH_LPT(dev)) {
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+ DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
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+ pipe);
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+ } else if (!is_cpu_edp) {
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struct intel_pch_pll *pll;
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pll = intel_get_pch_pll(intel_crtc, dpll, fp);
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