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@@ -1,5 +1,5 @@
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/*
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/*
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- * linux/drivers/ide/pci/hpt366.c Version 1.04 Jun 4, 2007
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+ * linux/drivers/ide/pci/hpt366.c Version 1.06 Jun 27, 2007
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*
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*
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* Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
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* Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
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* Portions Copyright (C) 2001 Sun Microsystems, Inc.
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* Portions Copyright (C) 2001 Sun Microsystems, Inc.
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@@ -182,6 +182,7 @@ static const char *bad_ata66_4[] = {
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"IC35L040AVER07-0",
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"IC35L040AVER07-0",
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"IC35L060AVER07-0",
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"IC35L060AVER07-0",
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"WDC AC310200R",
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"WDC AC310200R",
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+ "MAXTOR STM3320620A",
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NULL
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NULL
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};
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};
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@@ -1513,18 +1514,28 @@ static int __devinit init_setup_hpt366(struct pci_dev *dev, ide_pci_device_t *d)
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goto init_single;
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goto init_single;
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/*
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/*
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- * HPT36x chips are single channel and
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- * do not seem to have the channel enable bit...
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+ * HPT36x chips have one channel per function and have
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+ * both channel enable bits located differently and visible
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+ * to both functions -- really stupid design decision... :-(
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+ * Bit 4 is for the primary channel, bit 5 for the secondary.
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*/
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*/
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d->channels = 1;
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d->channels = 1;
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- d->enablebits[0].reg = 0;
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+ d->enablebits[0].mask = d->enablebits[0].val = 0x10;
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if ((dev2 = pci_get_slot(dev->bus, dev->devfn + 1)) != NULL) {
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if ((dev2 = pci_get_slot(dev->bus, dev->devfn + 1)) != NULL) {
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- u8 pin1 = 0, pin2 = 0;
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+ u8 mcr1 = 0, pin1 = 0, pin2 = 0;
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int ret;
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int ret;
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pci_set_drvdata(dev2, info[rev]);
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pci_set_drvdata(dev2, info[rev]);
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+ /*
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+ * Now we'll have to force both channels enabled if
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+ * at least one of them has been enabled by BIOS...
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+ */
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+ pci_read_config_byte(dev, 0x50, &mcr1);
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+ if (mcr1 & 0x30)
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+ pci_write_config_byte(dev, 0x50, mcr1 | 0x30);
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+
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pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
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pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
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pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2);
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pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2);
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if (pin1 != pin2 && dev->irq == dev2->irq) {
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if (pin1 != pin2 && dev->irq == dev2->irq) {
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