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@@ -89,6 +89,11 @@
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* affects i.MX25 and i.MX35.
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*/
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#define ESDHC_FLAG_ENGCM07207 BIT(2)
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+/*
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+ * The flag tells that the ESDHC controller is an USDHC block that is
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+ * integrated on the i.MX6 series.
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+ */
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+#define ESDHC_FLAG_USDHC BIT(3)
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enum imx_esdhc_type {
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IMX25_ESDHC,
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@@ -175,6 +180,11 @@ static inline int is_imx6q_usdhc(struct pltfm_imx_data *data)
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return data->devtype == IMX6Q_USDHC;
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}
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+static inline int esdhc_is_usdhc(struct pltfm_imx_data *data)
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+{
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+ return !!(data->flags & ESDHC_FLAG_USDHC);
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+}
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+
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static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
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{
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void __iomem *base = host->ioaddr + (reg & ~0x3);
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@@ -213,11 +223,11 @@ static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
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}
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}
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- if (unlikely(reg == SDHCI_CAPABILITIES_1) && is_imx6q_usdhc(imx_data))
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+ if (unlikely(reg == SDHCI_CAPABILITIES_1) && esdhc_is_usdhc(imx_data))
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val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104
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| SDHCI_SUPPORT_SDR50;
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- if (unlikely(reg == SDHCI_MAX_CURRENT) && is_imx6q_usdhc(imx_data)) {
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+ if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) {
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val = 0;
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val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT;
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val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT;
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@@ -307,7 +317,7 @@ static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
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if (unlikely(reg == SDHCI_HOST_VERSION)) {
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reg ^= 2;
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- if (is_imx6q_usdhc(imx_data)) {
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+ if (esdhc_is_usdhc(imx_data)) {
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/*
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* The usdhc register returns a wrong host version.
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* Correct it here.
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@@ -321,7 +331,7 @@ static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
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if (val & ESDHC_VENDOR_SPEC_VSELECT)
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ret |= SDHCI_CTRL_VDD_180;
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- if (is_imx6q_usdhc(imx_data)) {
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+ if (esdhc_is_usdhc(imx_data)) {
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val = readl(host->ioaddr + ESDHC_MIX_CTRL);
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if (val & ESDHC_MIX_CTRL_EXE_TUNE)
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ret |= SDHCI_CTRL_EXEC_TUNING;
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@@ -379,7 +389,7 @@ static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
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writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
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}
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- if (is_imx6q_usdhc(imx_data)) {
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+ if (esdhc_is_usdhc(imx_data)) {
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u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
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/* Swap AC23 bit */
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if (val & SDHCI_TRNS_AUTO_CMD23) {
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@@ -404,7 +414,7 @@ static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
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(imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
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imx_data->multiblock_status = MULTIBLK_IN_PROCESS;
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- if (is_imx6q_usdhc(imx_data))
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+ if (esdhc_is_usdhc(imx_data))
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writel(val << 16,
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host->ioaddr + SDHCI_TRANSFER_MODE);
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else
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@@ -470,7 +480,7 @@ static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
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* The reset on usdhc fails to clear MIX_CTRL register.
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* Do it manually here.
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*/
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- if (is_imx6q_usdhc(imx_data))
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+ if (esdhc_is_usdhc(imx_data))
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writel(0, host->ioaddr + ESDHC_MIX_CTRL);
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}
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}
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@@ -507,7 +517,7 @@ static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
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u32 temp, val;
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if (clock == 0) {
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- if (is_imx6q_usdhc(imx_data)) {
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+ if (esdhc_is_usdhc(imx_data)) {
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val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
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writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
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host->ioaddr + ESDHC_VENDOR_SPEC);
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@@ -515,7 +525,7 @@ static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
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goto out;
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}
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- if (is_imx6q_usdhc(imx_data))
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+ if (esdhc_is_usdhc(imx_data))
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pre_div = 1;
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temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
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@@ -542,7 +552,7 @@ static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
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| (pre_div << ESDHC_PREDIV_SHIFT));
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sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
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- if (is_imx6q_usdhc(imx_data)) {
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+ if (esdhc_is_usdhc(imx_data)) {
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val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
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writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
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host->ioaddr + ESDHC_VENDOR_SPEC);
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@@ -865,6 +875,9 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
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if (is_imx25_esdhc(imx_data) || is_imx35_esdhc(imx_data))
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imx_data->flags |= ESDHC_FLAG_ENGCM07207;
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+ if (is_imx6q_usdhc(imx_data))
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+ imx_data->flags |= ESDHC_FLAG_USDHC;
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+
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imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
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if (IS_ERR(imx_data->clk_ipg)) {
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err = PTR_ERR(imx_data->clk_ipg);
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@@ -917,7 +930,7 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
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* The imx6q ROM code will change the default watermark level setting
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* to something insane. Change it back here.
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*/
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- if (is_imx6q_usdhc(imx_data))
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+ if (esdhc_is_usdhc(imx_data))
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writel(0x08100810, host->ioaddr + ESDHC_WTMK_LVL);
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boarddata = &imx_data->boarddata;
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@@ -980,7 +993,7 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
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}
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/* sdr50 and sdr104 needs work on 1.8v signal voltage */
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- if ((boarddata->support_vsel) && is_imx6q_usdhc(imx_data)) {
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+ if ((boarddata->support_vsel) && esdhc_is_usdhc(imx_data)) {
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imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl,
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ESDHC_PINCTRL_STATE_100MHZ);
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imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl,
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