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@@ -99,17 +99,23 @@
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#define MSR_LE __MASK(MSR_LE_LG) /* Little Endian */
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#if defined(CONFIG_PPC_BOOK3S_64)
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+#define MSR_64BIT MSR_SF
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+
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/* Server variant */
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#define MSR_ MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_ISF |MSR_HV
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-#define MSR_KERNEL MSR_ | MSR_SF
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+#define MSR_KERNEL MSR_ | MSR_64BIT
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#define MSR_USER32 MSR_ | MSR_PR | MSR_EE
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-#define MSR_USER64 MSR_USER32 | MSR_SF
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+#define MSR_USER64 MSR_USER32 | MSR_64BIT
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#elif defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_8xx)
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/* Default MSR for kernel mode. */
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#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR)
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#define MSR_USER (MSR_KERNEL|MSR_PR|MSR_EE)
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#endif
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+#ifndef MSR_64BIT
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+#define MSR_64BIT 0
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+#endif
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+
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/* Floating Point Status and Control Register (FPSCR) Fields */
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#define FPSCR_FX 0x80000000 /* FPU exception summary */
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#define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */
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