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@@ -267,7 +267,7 @@ static void pch_spi_handler_sub(struct pch_spi_data *data, u32 reg_spsr_val,
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if (reg_spsr_val & SPSR_FI_BIT) {
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if (reg_spsr_val & SPSR_FI_BIT) {
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/* disable FI & RFI interrupts */
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/* disable FI & RFI interrupts */
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pch_spi_setclr_reg(data->master, PCH_SPCR, 0,
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pch_spi_setclr_reg(data->master, PCH_SPCR, 0,
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- SPCR_FIE_BIT | SPCR_TFIE_BIT);
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+ SPCR_FIE_BIT | SPCR_RFIE_BIT);
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/* transfer is completed;inform pch_spi_process_messages */
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/* transfer is completed;inform pch_spi_process_messages */
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data->transfer_complete = true;
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data->transfer_complete = true;
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@@ -679,11 +679,11 @@ static void pch_spi_set_ir(struct pch_spi_data *data)
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if ((data->bpw_len) > PCH_MAX_FIFO_DEPTH) {
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if ((data->bpw_len) > PCH_MAX_FIFO_DEPTH) {
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/* set receive threhold to PCH_RX_THOLD */
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/* set receive threhold to PCH_RX_THOLD */
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pch_spi_setclr_reg(data->master, PCH_SPCR,
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pch_spi_setclr_reg(data->master, PCH_SPCR,
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- PCH_RX_THOLD << SPCR_TFIC_FIELD,
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- ~MASK_TFIC_SPCR_BITS);
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+ PCH_RX_THOLD << SPCR_RFIC_FIELD,
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+ ~MASK_RFIC_SPCR_BITS);
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/* enable FI and RFI interrupts */
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/* enable FI and RFI interrupts */
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pch_spi_setclr_reg(data->master, PCH_SPCR,
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pch_spi_setclr_reg(data->master, PCH_SPCR,
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- SPCR_RFIE_BIT | SPCR_TFIE_BIT, 0);
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+ SPCR_RFIE_BIT | SPCR_FIE_BIT, 0);
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} else {
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} else {
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/* set receive threhold to maximum */
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/* set receive threhold to maximum */
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pch_spi_setclr_reg(data->master, PCH_SPCR,
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pch_spi_setclr_reg(data->master, PCH_SPCR,
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