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@@ -11130,7 +11130,7 @@ intel_display_capture_error_state(struct drm_device *dev)
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if (INTEL_INFO(dev)->num_pipes == 0)
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return NULL;
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- error = kmalloc(sizeof(*error), GFP_ATOMIC);
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+ error = kzalloc(sizeof(*error), GFP_ATOMIC);
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if (error == NULL)
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return NULL;
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@@ -11138,6 +11138,9 @@ intel_display_capture_error_state(struct drm_device *dev)
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error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
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for_each_pipe(i) {
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+ if (!intel_display_power_enabled(dev, POWER_DOMAIN_PIPE(i)))
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+ continue;
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+
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if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
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error->cursor[i].control = I915_READ(CURCNTR(i));
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error->cursor[i].position = I915_READ(CURPOS(i));
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@@ -11171,6 +11174,10 @@ intel_display_capture_error_state(struct drm_device *dev)
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for (i = 0; i < error->num_transcoders; i++) {
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enum transcoder cpu_transcoder = transcoders[i];
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+ if (!intel_display_power_enabled(dev,
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+ POWER_DOMAIN_TRANSCODER(cpu_transcoder)))
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+ continue;
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+
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error->transcoder[i].cpu_transcoder = cpu_transcoder;
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error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
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@@ -11182,12 +11189,6 @@ intel_display_capture_error_state(struct drm_device *dev)
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error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
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}
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- /* In the code above we read the registers without checking if the power
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- * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
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- * prevent the next I915_WRITE from detecting it and printing an error
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- * message. */
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- intel_uncore_clear_errors(dev);
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-
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return error;
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}
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