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@@ -116,22 +116,6 @@ TODO:
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#define PCI9111_8254_CLOCK_PERIOD_NS 500
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-#define PCI9111_8254_COUNTER_0 0x00
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-#define PCI9111_8254_COUNTER_1 0x40
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-#define PCI9111_8254_COUNTER_2 0x80
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-#define PCI9111_8254_COUNTER_LATCH 0x00
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-#define PCI9111_8254_READ_LOAD_LSB_ONLY 0x10
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-#define PCI9111_8254_READ_LOAD_MSB_ONLY 0x20
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-#define PCI9111_8254_READ_LOAD_LSB_MSB 0x30
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-#define PCI9111_8254_MODE_0 0x00
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-#define PCI9111_8254_MODE_1 0x02
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-#define PCI9111_8254_MODE_2 0x04
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-#define PCI9111_8254_MODE_3 0x06
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-#define PCI9111_8254_MODE_4 0x08
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-#define PCI9111_8254_MODE_5 0x0A
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-#define PCI9111_8254_BINARY_COUNTER 0x00
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-#define PCI9111_8254_BCD_COUNTER 0x01
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-
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/* IO address map */
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#define PCI9111_REGISTER_AD_FIFO_VALUE 0x00 /* AD Data stored
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@@ -148,10 +132,7 @@ TODO:
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#define PCI9111_REGISTER_AD_MODE_INTERRUPT_READBACK 0x0A
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#define PCI9111_REGISTER_SOFTWARE_TRIGGER 0x0E
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#define PCI9111_REGISTER_INTERRUPT_CONTROL 0x0C
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-#define PCI9111_REGISTER_8254_COUNTER_0 0x40
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-#define PCI9111_REGISTER_8254_COUNTER_1 0x42
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-#define PCI9111_REGISTER_8254_COUNTER_2 0X44
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-#define PCI9111_REGISTER_8254_CONTROL 0x46
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+#define PCI9111_8254_BASE_REG 0x40
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#define PCI9111_REGISTER_INTERRUPT_CLEAR 0x48
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#define PCI9111_TRIGGER_MASK 0x0F
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@@ -379,36 +360,16 @@ static void plx9050_interrupt_control(unsigned long io_base,
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static void pci9111_timer_set(struct comedi_device *dev)
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{
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struct pci9111_private_data *dev_private = dev->private;
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+ unsigned long timer_base = dev->iobase + PCI9111_8254_BASE_REG;
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- outb(PCI9111_8254_COUNTER_0 |
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- PCI9111_8254_READ_LOAD_LSB_MSB |
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- PCI9111_8254_MODE_0 |
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- PCI9111_8254_BINARY_COUNTER,
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- dev->iobase + PCI9111_REGISTER_8254_CONTROL);
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-
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- outb(PCI9111_8254_COUNTER_1 |
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- PCI9111_8254_READ_LOAD_LSB_MSB |
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- PCI9111_8254_MODE_2 |
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- PCI9111_8254_BINARY_COUNTER,
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- dev->iobase + PCI9111_REGISTER_8254_CONTROL);
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-
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- outb(PCI9111_8254_COUNTER_2 |
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- PCI9111_8254_READ_LOAD_LSB_MSB |
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- PCI9111_8254_MODE_2 |
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- PCI9111_8254_BINARY_COUNTER,
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- dev->iobase + PCI9111_REGISTER_8254_CONTROL);
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+ i8254_set_mode(timer_base, 1, 0, I8254_MODE0 | I8254_BINARY);
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+ i8254_set_mode(timer_base, 1, 1, I8254_MODE2 | I8254_BINARY);
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+ i8254_set_mode(timer_base, 1, 2, I8254_MODE2 | I8254_BINARY);
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udelay(1);
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- outb(dev_private->timer_divisor_2 & 0xff,
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- dev->iobase + PCI9111_REGISTER_8254_COUNTER_2);
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- outb((dev_private->timer_divisor_2 >> 8) & 0xff,
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- dev->iobase + PCI9111_REGISTER_8254_COUNTER_2);
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-
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- outb(dev_private->timer_divisor_1 & 0xff,
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- dev->iobase + PCI9111_REGISTER_8254_COUNTER_1);
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- outb((dev_private->timer_divisor_1 >> 8) & 0xff,
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- dev->iobase + PCI9111_REGISTER_8254_COUNTER_1);
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+ i8254_write(timer_base, 1, 2, dev_private->timer_divisor_2);
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+ i8254_write(timer_base, 1, 1, dev_private->timer_divisor_1);
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}
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enum pci9111_trigger_sources {
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