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+/*
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+ * Toumaz Xenif TZ1090 GPIO handling.
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+ *
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+ * Copyright (C) 2008-2013 Imagination Technologies Ltd.
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+ *
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+ * Based on ARM PXA code and others.
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ */
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+
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+#include <linux/bitops.h>
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+#include <linux/export.h>
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+#include <linux/gpio.h>
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+#include <linux/interrupt.h>
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+#include <linux/io.h>
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+#include <linux/irq.h>
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+#include <linux/irqdomain.h>
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+#include <linux/kernel.h>
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+#include <linux/of_irq.h>
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+#include <linux/pinctrl/consumer.h>
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+#include <linux/platform_device.h>
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+#include <linux/slab.h>
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+#include <linux/syscore_ops.h>
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+#include <asm/global_lock.h>
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+
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+/* Register offsets from bank base address */
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+#define REG_GPIO_DIR 0x00
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+#define REG_GPIO_IRQ_PLRT 0x20
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+#define REG_GPIO_IRQ_TYPE 0x30
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+#define REG_GPIO_IRQ_EN 0x40
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+#define REG_GPIO_IRQ_STS 0x50
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+#define REG_GPIO_BIT_EN 0x60
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+#define REG_GPIO_DIN 0x70
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+#define REG_GPIO_DOUT 0x80
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+
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+/* REG_GPIO_IRQ_PLRT */
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+#define REG_GPIO_IRQ_PLRT_LOW 0
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+#define REG_GPIO_IRQ_PLRT_HIGH 1
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+
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+/* REG_GPIO_IRQ_TYPE */
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+#define REG_GPIO_IRQ_TYPE_LEVEL 0
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+#define REG_GPIO_IRQ_TYPE_EDGE 1
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+
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+/**
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+ * struct tz1090_gpio_bank - GPIO bank private data
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+ * @chip: Generic GPIO chip for GPIO bank
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+ * @domain: IRQ domain for GPIO bank (may be NULL)
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+ * @reg: Base of registers, offset for this GPIO bank
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+ * @irq: IRQ number for GPIO bank
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+ * @label: Debug GPIO bank label, used for storage of chip->label
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+ *
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+ * This is the main private data for a GPIO bank. It encapsulates a gpio_chip,
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+ * and the callbacks for the gpio_chip can access the private data with the
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+ * to_bank() macro below.
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+ */
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+struct tz1090_gpio_bank {
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+ struct gpio_chip chip;
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+ struct irq_domain *domain;
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+ void __iomem *reg;
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+ int irq;
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+ char label[16];
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+};
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+#define to_bank(c) container_of(c, struct tz1090_gpio_bank, chip)
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+
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+/**
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+ * struct tz1090_gpio - Overall GPIO device private data
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+ * @dev: Device (from platform device)
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+ * @reg: Base of GPIO registers
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+ *
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+ * Represents the overall GPIO device. This structure is actually only
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+ * temporary, and used during init.
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+ */
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+struct tz1090_gpio {
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+ struct device *dev;
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+ void __iomem *reg;
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+};
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+
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+/**
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+ * struct tz1090_gpio_bank_info - Temporary registration info for GPIO bank
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+ * @priv: Overall GPIO device private data
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+ * @node: Device tree node specific to this GPIO bank
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+ * @index: Index of bank in range 0-2
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+ */
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+struct tz1090_gpio_bank_info {
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+ struct tz1090_gpio *priv;
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+ struct device_node *node;
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+ unsigned int index;
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+};
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+
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+/* Convenience register accessors */
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+static inline void tz1090_gpio_write(struct tz1090_gpio_bank *bank,
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+ unsigned int reg_offs, u32 data)
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+{
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+ iowrite32(data, bank->reg + reg_offs);
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+}
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+
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+static inline u32 tz1090_gpio_read(struct tz1090_gpio_bank *bank,
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+ unsigned int reg_offs)
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+{
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+ return ioread32(bank->reg + reg_offs);
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+}
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+
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+/* caller must hold LOCK2 */
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+static inline void _tz1090_gpio_clear_bit(struct tz1090_gpio_bank *bank,
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+ unsigned int reg_offs,
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+ unsigned int offset)
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+{
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+ u32 value;
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+
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+ value = tz1090_gpio_read(bank, reg_offs);
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+ value &= ~BIT(offset);
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+ tz1090_gpio_write(bank, reg_offs, value);
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+}
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+
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+static void tz1090_gpio_clear_bit(struct tz1090_gpio_bank *bank,
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+ unsigned int reg_offs,
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+ unsigned int offset)
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+{
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+ int lstat;
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+
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+ __global_lock2(lstat);
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+ _tz1090_gpio_clear_bit(bank, reg_offs, offset);
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+ __global_unlock2(lstat);
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+}
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+
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+/* caller must hold LOCK2 */
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+static inline void _tz1090_gpio_set_bit(struct tz1090_gpio_bank *bank,
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+ unsigned int reg_offs,
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+ unsigned int offset)
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+{
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+ u32 value;
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+
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+ value = tz1090_gpio_read(bank, reg_offs);
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+ value |= BIT(offset);
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+ tz1090_gpio_write(bank, reg_offs, value);
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+}
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+
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+static void tz1090_gpio_set_bit(struct tz1090_gpio_bank *bank,
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+ unsigned int reg_offs,
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+ unsigned int offset)
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+{
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+ int lstat;
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+
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+ __global_lock2(lstat);
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+ _tz1090_gpio_set_bit(bank, reg_offs, offset);
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+ __global_unlock2(lstat);
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+}
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+
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+/* caller must hold LOCK2 */
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+static inline void _tz1090_gpio_mod_bit(struct tz1090_gpio_bank *bank,
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+ unsigned int reg_offs,
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+ unsigned int offset,
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+ bool val)
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+{
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+ u32 value;
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+
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+ value = tz1090_gpio_read(bank, reg_offs);
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+ value &= ~BIT(offset);
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+ if (val)
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+ value |= BIT(offset);
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+ tz1090_gpio_write(bank, reg_offs, value);
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+}
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+
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+static void tz1090_gpio_mod_bit(struct tz1090_gpio_bank *bank,
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+ unsigned int reg_offs,
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+ unsigned int offset,
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+ bool val)
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+{
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+ int lstat;
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+
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+ __global_lock2(lstat);
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+ _tz1090_gpio_mod_bit(bank, reg_offs, offset, val);
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+ __global_unlock2(lstat);
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+}
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+
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+static inline int tz1090_gpio_read_bit(struct tz1090_gpio_bank *bank,
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+ unsigned int reg_offs,
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+ unsigned int offset)
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+{
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+ return tz1090_gpio_read(bank, reg_offs) & BIT(offset);
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+}
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+
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+/* GPIO chip callbacks */
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+
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+static int tz1090_gpio_direction_input(struct gpio_chip *chip,
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+ unsigned int offset)
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+{
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+ struct tz1090_gpio_bank *bank = to_bank(chip);
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+ tz1090_gpio_set_bit(bank, REG_GPIO_DIR, offset);
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+
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+ return 0;
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+}
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+
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+static int tz1090_gpio_direction_output(struct gpio_chip *chip,
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+ unsigned int offset, int output_value)
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+{
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+ struct tz1090_gpio_bank *bank = to_bank(chip);
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+ int lstat;
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+
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+ __global_lock2(lstat);
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+ _tz1090_gpio_mod_bit(bank, REG_GPIO_DOUT, offset, output_value);
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+ _tz1090_gpio_clear_bit(bank, REG_GPIO_DIR, offset);
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+ __global_unlock2(lstat);
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+
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+ return 0;
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+}
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+
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+/*
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+ * Return GPIO level
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+ */
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+static int tz1090_gpio_get(struct gpio_chip *chip, unsigned int offset)
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+{
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+ struct tz1090_gpio_bank *bank = to_bank(chip);
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+
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+ return tz1090_gpio_read_bit(bank, REG_GPIO_DIN, offset);
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+}
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+
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+/*
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+ * Set output GPIO level
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+ */
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+static void tz1090_gpio_set(struct gpio_chip *chip, unsigned int offset,
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+ int output_value)
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+{
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+ struct tz1090_gpio_bank *bank = to_bank(chip);
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+
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+ tz1090_gpio_mod_bit(bank, REG_GPIO_DOUT, offset, output_value);
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+}
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+
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+static int tz1090_gpio_request(struct gpio_chip *chip, unsigned int offset)
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+{
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+ struct tz1090_gpio_bank *bank = to_bank(chip);
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+ int ret;
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+
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+ ret = pinctrl_request_gpio(chip->base + offset);
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+ if (ret)
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+ return ret;
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+
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+ tz1090_gpio_set_bit(bank, REG_GPIO_DIR, offset);
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+ tz1090_gpio_set_bit(bank, REG_GPIO_BIT_EN, offset);
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+
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+ return 0;
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+}
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+
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+static void tz1090_gpio_free(struct gpio_chip *chip, unsigned int offset)
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+{
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+ struct tz1090_gpio_bank *bank = to_bank(chip);
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+
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+ pinctrl_free_gpio(chip->base + offset);
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+
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+ tz1090_gpio_clear_bit(bank, REG_GPIO_BIT_EN, offset);
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+}
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+
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+static int tz1090_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
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+{
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+ struct tz1090_gpio_bank *bank = to_bank(chip);
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+
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+ if (!bank->domain)
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+ return -EINVAL;
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+
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+ return irq_create_mapping(bank->domain, offset);
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+}
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+
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+/* IRQ chip handlers */
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+
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+/* Get TZ1090 GPIO chip from irq data provided to generic IRQ callbacks */
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+static inline struct tz1090_gpio_bank *irqd_to_gpio_bank(struct irq_data *data)
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+{
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+ return (struct tz1090_gpio_bank *)data->domain->host_data;
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+}
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+
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+static void tz1090_gpio_irq_clear(struct tz1090_gpio_bank *bank,
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+ unsigned int offset)
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+{
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+ tz1090_gpio_clear_bit(bank, REG_GPIO_IRQ_STS, offset);
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+}
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+
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+static void tz1090_gpio_irq_enable(struct tz1090_gpio_bank *bank,
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+ unsigned int offset, bool enable)
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+{
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+ tz1090_gpio_mod_bit(bank, REG_GPIO_IRQ_EN, offset, enable);
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+}
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+
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+static void tz1090_gpio_irq_polarity(struct tz1090_gpio_bank *bank,
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+ unsigned int offset, unsigned int polarity)
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+{
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+ tz1090_gpio_mod_bit(bank, REG_GPIO_IRQ_PLRT, offset, polarity);
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+}
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+
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+static int tz1090_gpio_valid_handler(struct irq_desc *desc)
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+{
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+ return desc->handle_irq == handle_level_irq ||
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+ desc->handle_irq == handle_edge_irq;
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+}
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+
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+static void tz1090_gpio_irq_type(struct tz1090_gpio_bank *bank,
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+ unsigned int offset, unsigned int type)
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+{
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+ tz1090_gpio_mod_bit(bank, REG_GPIO_IRQ_TYPE, offset, type);
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+}
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+
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+/* set polarity to trigger on next edge, whether rising or falling */
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+static void tz1090_gpio_irq_next_edge(struct tz1090_gpio_bank *bank,
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+ unsigned int offset)
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+{
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+ unsigned int value_p, value_i;
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+ int lstat;
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+
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+ /*
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+ * Set the GPIO's interrupt polarity to the opposite of the current
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+ * input value so that the next edge triggers an interrupt.
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+ */
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+ __global_lock2(lstat);
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+ value_i = ~tz1090_gpio_read(bank, REG_GPIO_DIN);
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+ value_p = tz1090_gpio_read(bank, REG_GPIO_IRQ_PLRT);
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+ value_p &= ~BIT(offset);
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+ value_p |= value_i & BIT(offset);
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+ tz1090_gpio_write(bank, REG_GPIO_IRQ_PLRT, value_p);
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+ __global_unlock2(lstat);
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+}
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+
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+static void gpio_ack_irq(struct irq_data *data)
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+{
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+ struct tz1090_gpio_bank *bank = irqd_to_gpio_bank(data);
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+
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+ tz1090_gpio_irq_clear(bank, data->hwirq);
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+}
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+
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+static void gpio_mask_irq(struct irq_data *data)
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+{
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+ struct tz1090_gpio_bank *bank = irqd_to_gpio_bank(data);
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+
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+ tz1090_gpio_irq_enable(bank, data->hwirq, false);
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+}
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+
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+static void gpio_unmask_irq(struct irq_data *data)
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+{
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+ struct tz1090_gpio_bank *bank = irqd_to_gpio_bank(data);
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+
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+ tz1090_gpio_irq_enable(bank, data->hwirq, true);
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+}
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+
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+static unsigned int gpio_startup_irq(struct irq_data *data)
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+{
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+ struct tz1090_gpio_bank *bank = irqd_to_gpio_bank(data);
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+ irq_hw_number_t hw = data->hwirq;
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+ struct irq_desc *desc = irq_to_desc(data->irq);
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+
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+ /*
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+ * This warning indicates that the type of the irq hasn't been set
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+ * before enabling the irq. This would normally be done by passing some
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+ * trigger flags to request_irq().
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+ */
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+ WARN(!tz1090_gpio_valid_handler(desc),
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+ "irq type not set before enabling gpio irq %d", data->irq);
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+
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+ tz1090_gpio_irq_clear(bank, hw);
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+ tz1090_gpio_irq_enable(bank, hw, true);
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+ return 0;
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+}
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+
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+static int gpio_set_irq_type(struct irq_data *data, unsigned int flow_type)
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+{
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+ struct tz1090_gpio_bank *bank = irqd_to_gpio_bank(data);
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+ unsigned int type;
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+ unsigned int polarity;
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+
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+ switch (flow_type) {
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+ case IRQ_TYPE_EDGE_BOTH:
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+ type = REG_GPIO_IRQ_TYPE_EDGE;
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+ polarity = REG_GPIO_IRQ_PLRT_LOW;
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+ break;
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+ case IRQ_TYPE_EDGE_RISING:
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+ type = REG_GPIO_IRQ_TYPE_EDGE;
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+ polarity = REG_GPIO_IRQ_PLRT_HIGH;
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+ break;
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+ case IRQ_TYPE_EDGE_FALLING:
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+ type = REG_GPIO_IRQ_TYPE_EDGE;
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+ polarity = REG_GPIO_IRQ_PLRT_LOW;
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+ break;
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+ case IRQ_TYPE_LEVEL_HIGH:
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+ type = REG_GPIO_IRQ_TYPE_LEVEL;
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+ polarity = REG_GPIO_IRQ_PLRT_HIGH;
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+ break;
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+ case IRQ_TYPE_LEVEL_LOW:
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+ type = REG_GPIO_IRQ_TYPE_LEVEL;
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+ polarity = REG_GPIO_IRQ_PLRT_LOW;
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+ break;
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+ default:
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+ return -EINVAL;
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+ }
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+
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+ tz1090_gpio_irq_type(bank, data->hwirq, type);
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+ if (type == REG_GPIO_IRQ_TYPE_LEVEL)
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+ __irq_set_handler_locked(data->irq, handle_level_irq);
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+ else
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+ __irq_set_handler_locked(data->irq, handle_edge_irq);
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+
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+ if (flow_type == IRQ_TYPE_EDGE_BOTH)
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+ tz1090_gpio_irq_next_edge(bank, data->hwirq);
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+ else
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+ tz1090_gpio_irq_polarity(bank, data->hwirq, polarity);
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+
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+ return 0;
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+}
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+
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+#ifdef CONFIG_SUSPEND
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+static int gpio_set_irq_wake(struct irq_data *data, unsigned int on)
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+{
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+ struct tz1090_gpio_bank *bank = irqd_to_gpio_bank(data);
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+
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+#ifdef CONFIG_PM_DEBUG
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+ pr_info("irq_wake irq%d state:%d\n", data->irq, on);
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+#endif
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+
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+ /* wake on gpio block interrupt */
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+ return irq_set_irq_wake(bank->irq, on);
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+}
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+#else
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+#define gpio_set_irq_wake NULL
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+#endif
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+
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+/* gpio virtual interrupt functions */
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+static struct irq_chip gpio_irq_chip = {
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+ .irq_startup = gpio_startup_irq,
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+ .irq_ack = gpio_ack_irq,
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+ .irq_mask = gpio_mask_irq,
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+ .irq_unmask = gpio_unmask_irq,
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+ .irq_set_type = gpio_set_irq_type,
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+ .irq_set_wake = gpio_set_irq_wake,
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+ .flags = IRQCHIP_MASK_ON_SUSPEND,
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+};
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+
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+static void tz1090_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
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+{
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+ irq_hw_number_t hw;
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+ unsigned int irq_stat, irq_no;
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+ struct tz1090_gpio_bank *bank;
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+ struct irq_desc *child_desc;
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+
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+ bank = (struct tz1090_gpio_bank *)irq_desc_get_handler_data(desc);
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+ irq_stat = tz1090_gpio_read(bank, REG_GPIO_DIR) &
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+ tz1090_gpio_read(bank, REG_GPIO_IRQ_STS) &
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+ tz1090_gpio_read(bank, REG_GPIO_IRQ_EN) &
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+ 0x3FFFFFFF; /* 30 bits only */
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+
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+ for (hw = 0; irq_stat; irq_stat >>= 1, ++hw) {
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+ if (!(irq_stat & 1))
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+ continue;
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+
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+ irq_no = irq_linear_revmap(bank->domain, hw);
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+ child_desc = irq_to_desc(irq_no);
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+
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+ /* Toggle edge for pin with both edges triggering enabled */
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+ if (irqd_get_trigger_type(&child_desc->irq_data)
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+ == IRQ_TYPE_EDGE_BOTH)
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+ tz1090_gpio_irq_next_edge(bank, hw);
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+
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+ BUG_ON(!tz1090_gpio_valid_handler(child_desc));
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+ generic_handle_irq_desc(irq_no, child_desc);
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+ }
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+}
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+
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+static int tz1090_gpio_irq_map(struct irq_domain *d, unsigned int irq,
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+ irq_hw_number_t hw)
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+{
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+ irq_set_chip(irq, &gpio_irq_chip);
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+ return 0;
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+}
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+
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+static const struct irq_domain_ops tz1090_gpio_irq_domain_ops = {
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+ .map = tz1090_gpio_irq_map,
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+ .xlate = irq_domain_xlate_twocell,
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+};
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+
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+static int tz1090_gpio_bank_probe(struct tz1090_gpio_bank_info *info)
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+{
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+ struct device_node *np = info->node;
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+ struct device *dev = info->priv->dev;
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+ struct tz1090_gpio_bank *bank;
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+
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+ bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
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+ if (!bank) {
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+ dev_err(dev, "unable to allocate driver data\n");
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+ return -ENOMEM;
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+ }
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+
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+ /* Offset the main registers to the first register in this bank */
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+ bank->reg = info->priv->reg + info->index * 4;
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+
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+ /* Set up GPIO chip */
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+ snprintf(bank->label, sizeof(bank->label), "tz1090-gpio-%u",
|
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+ info->index);
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+ bank->chip.label = bank->label;
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+ bank->chip.dev = dev;
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+ bank->chip.direction_input = tz1090_gpio_direction_input;
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+ bank->chip.direction_output = tz1090_gpio_direction_output;
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+ bank->chip.get = tz1090_gpio_get;
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+ bank->chip.set = tz1090_gpio_set;
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+ bank->chip.free = tz1090_gpio_free;
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+ bank->chip.request = tz1090_gpio_request;
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+ bank->chip.to_irq = tz1090_gpio_to_irq;
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|
|
+ bank->chip.of_node = np;
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+
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|
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+ /* GPIO numbering from 0 */
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|
|
+ bank->chip.base = info->index * 30;
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|
|
+ bank->chip.ngpio = 30;
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+
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|
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+ /* Add the GPIO bank */
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|
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+ gpiochip_add(&bank->chip);
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+
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|
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+ /* Get the GPIO bank IRQ if provided */
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|
|
+ bank->irq = irq_of_parse_and_map(np, 0);
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|
|
+
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|
|
+ /* The interrupt is optional (it may be used by another core on chip) */
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|
|
+ if (bank->irq < 0) {
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|
|
+ dev_info(dev, "IRQ not provided for bank %u, IRQs disabled\n",
|
|
|
+ info->index);
|
|
|
+ return 0;
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|
|
+ }
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|
|
+
|
|
|
+ dev_info(dev, "Setting up IRQs for GPIO bank %u\n",
|
|
|
+ info->index);
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|
|
+
|
|
|
+ /*
|
|
|
+ * Initialise all interrupts to disabled so we don't get
|
|
|
+ * spurious ones on a dirty boot and hit the BUG_ON in the
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|
+ * handler.
|
|
|
+ */
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|
|
+ tz1090_gpio_write(bank, REG_GPIO_IRQ_EN, 0);
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|
|
+
|
|
|
+ /* Add a virtual IRQ for each GPIO */
|
|
|
+ bank->domain = irq_domain_add_linear(np,
|
|
|
+ bank->chip.ngpio,
|
|
|
+ &tz1090_gpio_irq_domain_ops,
|
|
|
+ bank);
|
|
|
+
|
|
|
+ /* Setup chained handler for this GPIO bank */
|
|
|
+ irq_set_handler_data(bank->irq, bank);
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|
|
+ irq_set_chained_handler(bank->irq, tz1090_gpio_irq_handler);
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|
|
+
|
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|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static void tz1090_gpio_register_banks(struct tz1090_gpio *priv)
|
|
|
+{
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|
|
+ struct device_node *np = priv->dev->of_node;
|
|
|
+ struct device_node *node;
|
|
|
+
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|
|
+ for_each_available_child_of_node(np, node) {
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|
|
+ struct tz1090_gpio_bank_info info;
|
|
|
+ u32 addr;
|
|
|
+ int ret;
|
|
|
+
|
|
|
+ ret = of_property_read_u32(node, "reg", &addr);
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|
|
+ if (ret) {
|
|
|
+ dev_err(priv->dev, "invalid reg on %s\n",
|
|
|
+ node->full_name);
|
|
|
+ continue;
|
|
|
+ }
|
|
|
+ if (addr >= 3) {
|
|
|
+ dev_err(priv->dev, "index %u in %s out of range\n",
|
|
|
+ addr, node->full_name);
|
|
|
+ continue;
|
|
|
+ }
|
|
|
+
|
|
|
+ info.index = addr;
|
|
|
+ info.node = of_node_get(node);
|
|
|
+ info.priv = priv;
|
|
|
+
|
|
|
+ ret = tz1090_gpio_bank_probe(&info);
|
|
|
+ if (ret) {
|
|
|
+ dev_err(priv->dev, "failure registering %s\n",
|
|
|
+ node->full_name);
|
|
|
+ of_node_put(node);
|
|
|
+ continue;
|
|
|
+ }
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+static int tz1090_gpio_probe(struct platform_device *pdev)
|
|
|
+{
|
|
|
+ struct device_node *np = pdev->dev.of_node;
|
|
|
+ struct resource *res_regs;
|
|
|
+ struct tz1090_gpio priv;
|
|
|
+
|
|
|
+ if (!np) {
|
|
|
+ dev_err(&pdev->dev, "must be instantiated via devicetree\n");
|
|
|
+ return -ENOENT;
|
|
|
+ }
|
|
|
+
|
|
|
+ res_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
+ if (!res_regs) {
|
|
|
+ dev_err(&pdev->dev, "cannot find registers resource\n");
|
|
|
+ return -ENOENT;
|
|
|
+ }
|
|
|
+
|
|
|
+ priv.dev = &pdev->dev;
|
|
|
+
|
|
|
+ /* Ioremap the registers */
|
|
|
+ priv.reg = devm_ioremap(&pdev->dev, res_regs->start,
|
|
|
+ res_regs->end - res_regs->start);
|
|
|
+ if (!priv.reg) {
|
|
|
+ dev_err(&pdev->dev, "unable to ioremap registers\n");
|
|
|
+ return -ENOMEM;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Look for banks */
|
|
|
+ tz1090_gpio_register_banks(&priv);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static struct of_device_id tz1090_gpio_of_match[] = {
|
|
|
+ { .compatible = "img,tz1090-gpio" },
|
|
|
+ { },
|
|
|
+};
|
|
|
+
|
|
|
+static struct platform_driver tz1090_gpio_driver = {
|
|
|
+ .driver = {
|
|
|
+ .name = "tz1090-gpio",
|
|
|
+ .owner = THIS_MODULE,
|
|
|
+ .of_match_table = tz1090_gpio_of_match,
|
|
|
+ },
|
|
|
+ .probe = tz1090_gpio_probe,
|
|
|
+};
|
|
|
+
|
|
|
+static int __init tz1090_gpio_init(void)
|
|
|
+{
|
|
|
+ return platform_driver_register(&tz1090_gpio_driver);
|
|
|
+}
|
|
|
+subsys_initcall(tz1090_gpio_init);
|