Merge master.kernel.org:/home/rmk/linux-2.6-arm

* master.kernel.org:/home/rmk/linux-2.6-arm: (38 commits)
  [ARM] 5191/1: ARM: remove CVS keywords
  [ARM] pxafb: fix the warning of incorrect lccr when lcd_conn is specified
  [ARM] pxafb: add flag to specify output format on LDD pins when base is RGBT16
  [ARM] pxafb: fix the incorrect configuration of GPIO77 as ACBIAS for TFT LCD
  [ARM] 5198/1: PalmTX: PCMCIA fixes
  [ARM] Fix a pile of broken watchdog drivers
  [ARM] update mach-types
  [ARM] 5196/1: fix inline asm constraints for preload
  [ARM] 5194/1: update .gitignore
  [ARM] add proc-macros.S include to proc-arm940 and proc-arm946
  [ARM] 5192/1: ARM TLB: add v7wbi_{possible,always}_flags to {possible,always}_tlb_flags
  [ARM] 5193/1: Wire up missing syscalls
  [ARM] traps: don't call undef hook functions with spinlock held
  [ARM] 5183/2: Provide Poodle LoCoMo GPIO names
  [ARM] dma-mapping: provide sync_range APIs
  [ARM] dma-mapping: improve type-safeness of DMA translations
  [ARM] Kirkwood: instantiate the orion_spi driver in the platform code
  [ARM] prevent crashing when too much RAM installed
  [ARM] Kirkwood: Instantiate mv_xor driver
  [ARM] Orion: Instantiate mv_xor driver for 5182
  ...

Documentation/arm/Samsung-S3C24XX/GPIO.txt

@@ -13,6 +13,21 @@ Introduction
   data-sheet/users manual to find out the complete list.
 
 
+GPIOLIB
+-------
+
+  With the event of the GPIOLIB in drivers/gpio, support for some
+  of the GPIO functions such as reading and writing a pin will
+  be removed in favour of this common access method.
+
+  Once all the extant drivers have been converted, the functions
+  listed below will be removed (they may be marked as __deprecated
+  in the near future).
+
+  - s3c2410_gpio_getpin
+  - s3c2410_gpio_setpin
+
+
 Headers
 -------
 

Documentation/arm/Samsung-S3C24XX/Overview.txt

@@ -8,9 +8,10 @@ Introduction
 
   The Samsung S3C24XX range of ARM9 System-on-Chip CPUs are supported
   by the 's3c2410' architecture of ARM Linux. Currently the S3C2410,
-  S3C2412, S3C2413, S3C2440 and S3C2442 devices are supported.
+  S3C2412, S3C2413, S3C2440, S3C2442 and S3C2443 devices are supported.
+
+  Support for the S3C2400 and S3C24A0 series are in progress.
 
-  Support for the S3C2400 series is in progress.
 
 Configuration
 -------------
@@ -38,6 +39,22 @@ Layout
   Register, kernel and platform data definitions are held in the
   arch/arm/mach-s3c2410 directory./include/mach
 
+arch/arm/plat-s3c24xx:
+
+  Files in here are either common to all the s3c24xx family,
+  or are common to only some of them with names to indicate this
+  status. The files that are not common to all are generally named
+  with the initial cpu they support in the series to ensure a short
+  name without any possibility of confusion with newer devices.
+
+  As an example, initially s3c244x would cover s3c2440 and s3c2442, but
+  with the s3c2443 which does not share many of the same drivers in
+  this directory, the name becomes invalid. We stick to s3c2440-<x>
+  to indicate a driver that is s3c2440 and s3c2442 compatible.
+
+  This does mean that to find the status of any given SoC, a number
+  of directories may need to be searched.
+
 
 Machines
 --------
@@ -159,6 +176,17 @@ NAND
   For more information see Documentation/arm/Samsung-S3C24XX/NAND.txt
 
 
+SD/MMC
+------
+
+  The SD/MMC hardware pre S3C2443 is supported in the current
+  kernel, the driver is drivers/mmc/host/s3cmci.c and supports
+  1 and 4 bit SD or MMC cards.
+
+  The SDIO behaviour of this driver has not been fully tested. There is no
+  current support for hardware SDIO interrupts.
+
+
 Serial
 ------
 
@@ -178,6 +206,9 @@ GPIO
   The core contains support for manipulating the GPIO, see the
   documentation in GPIO.txt in the same directory as this file.
 
+  Newer kernels carry GPIOLIB, and support is being moved towards
+  this with some of the older support in line to be removed.
+
 
 Clock Management
 ----------------

arch/arm/boot/compressed/.gitignore

@@ -1,2 +1,3 @@
-piggy.gz
 font.c
+piggy.gz
+vmlinux.lds

arch/arm/common/dmabounce.c

@@ -246,9 +246,9 @@ map_single(struct device *dev, void *ptr, size_t size,
 		}
 
 		dev_dbg(dev,
-			"%s: unsafe buffer %p (phy=%p) mapped to %p (phy=%p)\n",
-			__func__, buf->ptr, (void *) virt_to_dma(dev, buf->ptr),
-			buf->safe, (void *) buf->safe_dma_addr);
+			"%s: unsafe buffer %p (dma=%#x) mapped to %p (dma=%#x)\n",
+			__func__, buf->ptr, virt_to_dma(dev, buf->ptr),
+			buf->safe, buf->safe_dma_addr);
 
 		if ((dir == DMA_TO_DEVICE) ||
 		    (dir == DMA_BIDIRECTIONAL)) {
@@ -292,9 +292,9 @@ unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
 		BUG_ON(buf->size != size);
 
 		dev_dbg(dev,
-			"%s: unsafe buffer %p (phy=%p) mapped to %p (phy=%p)\n",
-			__func__, buf->ptr, (void *) virt_to_dma(dev, buf->ptr),
-			buf->safe, (void *) buf->safe_dma_addr);
+			"%s: unsafe buffer %p (dma=%#x) mapped to %p (dma=%#x)\n",
+			__func__, buf->ptr, virt_to_dma(dev, buf->ptr),
+			buf->safe, buf->safe_dma_addr);
 
 		DO_STATS ( device_info->bounce_count++ );
 
@@ -321,9 +321,8 @@ unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
 	}
 }
 
-static inline void
-sync_single(struct device *dev, dma_addr_t dma_addr, size_t size,
-		enum dma_data_direction dir)
+static int sync_single(struct device *dev, dma_addr_t dma_addr, size_t size,
+			enum dma_data_direction dir)
 {
 	struct dmabounce_device_info *device_info = dev->archdata.dmabounce;
 	struct safe_buffer *buf = NULL;
@@ -355,9 +354,9 @@ sync_single(struct device *dev, dma_addr_t dma_addr, size_t size,
 		 */
 
 		dev_dbg(dev,
-			"%s: unsafe buffer %p (phy=%p) mapped to %p (phy=%p)\n",
-			__func__, buf->ptr, (void *) virt_to_dma(dev, buf->ptr),
-			buf->safe, (void *) buf->safe_dma_addr);
+			"%s: unsafe buffer %p (dma=%#x) mapped to %p (dma=%#x)\n",
+			__func__, buf->ptr, virt_to_dma(dev, buf->ptr),
+			buf->safe, buf->safe_dma_addr);
 
 		DO_STATS ( device_info->bounce_count++ );
 
@@ -383,8 +382,9 @@ sync_single(struct device *dev, dma_addr_t dma_addr, size_t size,
 		 * No need to sync the safe buffer - it was allocated
 		 * via the coherent allocators.
 		 */
+		return 0;
 	} else {
-		dma_cache_maint(dma_to_virt(dev, dma_addr), size, dir);
+		return 1;
 	}
 }
 
@@ -474,25 +474,29 @@ dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
 	}
 }
 
-void
-dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_addr, size_t size,
-				enum dma_data_direction dir)
+void dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t dma_addr,
+				   unsigned long offset, size_t size,
+				   enum dma_data_direction dir)
 {
-	dev_dbg(dev, "%s(ptr=%p,size=%d,dir=%x)\n",
-		__func__, (void *) dma_addr, size, dir);
+	dev_dbg(dev, "%s(dma=%#x,off=%#lx,size=%zx,dir=%x)\n",
+		__func__, dma_addr, offset, size, dir);
 
-	sync_single(dev, dma_addr, size, dir);
+	if (sync_single(dev, dma_addr, offset + size, dir))
+		dma_cache_maint(dma_to_virt(dev, dma_addr) + offset, size, dir);
 }
+EXPORT_SYMBOL(dma_sync_single_range_for_cpu);
 
-void
-dma_sync_single_for_device(struct device *dev, dma_addr_t dma_addr, size_t size,
-				enum dma_data_direction dir)
+void dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_addr,
+				      unsigned long offset, size_t size,
+				      enum dma_data_direction dir)
 {
-	dev_dbg(dev, "%s(ptr=%p,size=%d,dir=%x)\n",
-		__func__, (void *) dma_addr, size, dir);
+	dev_dbg(dev, "%s(dma=%#x,off=%#lx,size=%zx,dir=%x)\n",
+		__func__, dma_addr, offset, size, dir);
 
-	sync_single(dev, dma_addr, size, dir);
+	if (sync_single(dev, dma_addr, offset + size, dir))
+		dma_cache_maint(dma_to_virt(dev, dma_addr) + offset, size, dir);
 }
+EXPORT_SYMBOL(dma_sync_single_range_for_device);
 
 void
 dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nents,
@@ -644,8 +648,6 @@ EXPORT_SYMBOL(dma_map_single);
 EXPORT_SYMBOL(dma_unmap_single);
 EXPORT_SYMBOL(dma_map_sg);
 EXPORT_SYMBOL(dma_unmap_sg);
-EXPORT_SYMBOL(dma_sync_single_for_cpu);
-EXPORT_SYMBOL(dma_sync_single_for_device);
 EXPORT_SYMBOL(dma_sync_sg_for_cpu);
 EXPORT_SYMBOL(dma_sync_sg_for_device);
 EXPORT_SYMBOL(dmabounce_register_dev);

arch/arm/configs/orion5x_defconfig

@@ -757,7 +757,14 @@ CONFIG_INPUT_EVDEV=y
 #
 # Input Device Drivers
 #
-# CONFIG_INPUT_KEYBOARD is not set
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+CONFIG_KEYBOARD_GPIO=y
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_INPUT_JOYSTICK is not set
 # CONFIG_INPUT_TABLET is not set
@@ -1111,11 +1118,11 @@ CONFIG_RTC_DRV_DS1307=y
 CONFIG_RTC_DRV_RS5C372=y
 # CONFIG_RTC_DRV_ISL1208 is not set
 # CONFIG_RTC_DRV_X1205 is not set
-# CONFIG_RTC_DRV_PCF8563 is not set
+CONFIG_RTC_DRV_PCF8563=y
 # CONFIG_RTC_DRV_PCF8583 is not set
 CONFIG_RTC_DRV_M41T80=y
 # CONFIG_RTC_DRV_M41T80_WDT is not set
-# CONFIG_RTC_DRV_S35390A is not set
+CONFIG_RTC_DRV_S35390A=y
 
 #
 # SPI RTC drivers

arch/arm/include/asm/dma-mapping.h

@@ -3,11 +3,48 @@
 
 #ifdef __KERNEL__
 
-#include <linux/mm.h> /* need struct page */
-
+#include <linux/mm_types.h>
 #include <linux/scatterlist.h>
 
 #include <asm-generic/dma-coherent.h>
+#include <asm/memory.h>
+
+/*
+ * page_to_dma/dma_to_virt/virt_to_dma are architecture private functions
+ * used internally by the DMA-mapping API to provide DMA addresses. They
+ * must not be used by drivers.
+ */
+#ifndef __arch_page_to_dma
+static inline dma_addr_t page_to_dma(struct device *dev, struct page *page)
+{
+	return (dma_addr_t)__virt_to_bus((unsigned long)page_address(page));
+}
+
+static inline void *dma_to_virt(struct device *dev, dma_addr_t addr)
+{
+	return (void *)__bus_to_virt(addr);
+}
+
+static inline dma_addr_t virt_to_dma(struct device *dev, void *addr)
+{
+	return (dma_addr_t)__virt_to_bus((unsigned long)(addr));
+}
+#else
+static inline dma_addr_t page_to_dma(struct device *dev, struct page *page)
+{
+	return __arch_page_to_dma(dev, page);
+}
+
+static inline void *dma_to_virt(struct device *dev, dma_addr_t addr)
+{
+	return __arch_dma_to_virt(dev, addr);
+}
+
+static inline dma_addr_t virt_to_dma(struct device *dev, void *addr)
+{
+	return __arch_virt_to_dma(dev, addr);
+}
+#endif
 
 /*
  * DMA-consistent mapping functions.  These allocate/free a region of
@@ -169,7 +206,7 @@ dma_map_single(struct device *dev, void *cpu_addr, size_t size,
 	if (!arch_is_coherent())
 		dma_cache_maint(cpu_addr, size, dir);
 
-	return virt_to_dma(dev, (unsigned long)cpu_addr);
+	return virt_to_dma(dev, cpu_addr);
 }
 #else
 extern dma_addr_t dma_map_single(struct device *,void *, size_t, enum dma_data_direction);
@@ -195,7 +232,7 @@ dma_map_page(struct device *dev, struct page *page,
 	     unsigned long offset, size_t size,
 	     enum dma_data_direction dir)
 {
-	return dma_map_single(dev, page_address(page) + offset, size, (int)dir);
+	return dma_map_single(dev, page_address(page) + offset, size, dir);
 }
 
 /**
@@ -241,7 +278,7 @@ static inline void
 dma_unmap_page(struct device *dev, dma_addr_t handle, size_t size,
 	       enum dma_data_direction dir)
 {
-	dma_unmap_single(dev, handle, size, (int)dir);
+	dma_unmap_single(dev, handle, size, dir);
 }
 
 /**
@@ -314,11 +351,12 @@ extern void dma_unmap_sg(struct device *, struct scatterlist *, int, enum dma_da
 
 
 /**
- * dma_sync_single_for_cpu
+ * dma_sync_single_range_for_cpu
  * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
  * @handle: DMA address of buffer
- * @size: size of buffer to map
- * @dir: DMA transfer direction
+ * @offset: offset of region to start sync
+ * @size: size of region to sync
+ * @dir: DMA transfer direction (same as passed to dma_map_single)
  *
  * Make physical memory consistent for a single streaming mode DMA
  * translation after a transfer.
@@ -332,25 +370,41 @@ extern void dma_unmap_sg(struct device *, struct scatterlist *, int, enum dma_da
  */
 #ifndef CONFIG_DMABOUNCE
 static inline void
-dma_sync_single_for_cpu(struct device *dev, dma_addr_t handle, size_t size,
-			enum dma_data_direction dir)
+dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t handle,
+			      unsigned long offset, size_t size,
+			      enum dma_data_direction dir)
 {
 	if (!arch_is_coherent())
-		dma_cache_maint((void *)dma_to_virt(dev, handle), size, dir);
+		dma_cache_maint(dma_to_virt(dev, handle) + offset, size, dir);
 }
 
 static inline void
-dma_sync_single_for_device(struct device *dev, dma_addr_t handle, size_t size,
-			   enum dma_data_direction dir)
+dma_sync_single_range_for_device(struct device *dev, dma_addr_t handle,
+				 unsigned long offset, size_t size,
+				 enum dma_data_direction dir)
 {
 	if (!arch_is_coherent())
-		dma_cache_maint((void *)dma_to_virt(dev, handle), size, dir);
+		dma_cache_maint(dma_to_virt(dev, handle) + offset, size, dir);
 }
 #else
-extern void dma_sync_single_for_cpu(struct device*, dma_addr_t, size_t, enum dma_data_direction);
-extern void dma_sync_single_for_device(struct device*, dma_addr_t, size_t, enum dma_data_direction);
+extern void dma_sync_single_range_for_cpu(struct device *, dma_addr_t, unsigned long, size_t, enum dma_data_direction);
+extern void dma_sync_single_range_for_device(struct device *, dma_addr_t, unsigned long, size_t, enum dma_data_direction);
 #endif
 
+static inline void
+dma_sync_single_for_cpu(struct device *dev, dma_addr_t handle, size_t size,
+			enum dma_data_direction dir)
+{
+	dma_sync_single_range_for_cpu(dev, handle, 0, size, dir);
+}
+
+static inline void
+dma_sync_single_for_device(struct device *dev, dma_addr_t handle, size_t size,
+			   enum dma_data_direction dir)
+{
+	dma_sync_single_range_for_device(dev, handle, 0, size, dir);
+}
+
 
 /**
  * dma_sync_sg_for_cpu

arch/arm/include/asm/memory.h

@@ -149,6 +149,14 @@
 #define arch_adjust_zones(node,size,holes) do { } while (0)
 #endif
 
+/*
+ * Amount of memory reserved for the vmalloc() area, and minimum
+ * address for vmalloc mappings.
+ */
+extern unsigned long vmalloc_reserve;
+
+#define VMALLOC_MIN		(void *)(VMALLOC_END - vmalloc_reserve)
+
 /*
  * PFNs are used to describe any physical page; this means
  * PFN 0 == physical address 0.
@@ -305,20 +313,6 @@ static inline __deprecated void *bus_to_virt(unsigned long x)
  */
 #define page_to_phys(page)	(page_to_pfn(page) << PAGE_SHIFT)
 
-/*
- * Optional device DMA address remapping. Do _not_ use directly!
- * We should really eliminate virt_to_bus() here - it's deprecated.
- */
-#ifndef __arch_page_to_dma
-#define page_to_dma(dev, page)		((dma_addr_t)__virt_to_bus((unsigned long)page_address(page)))
-#define dma_to_virt(dev, addr)		((void *)__bus_to_virt(addr))
-#define virt_to_dma(dev, addr)		((dma_addr_t)__virt_to_bus((unsigned long)(addr)))
-#else
-#define page_to_dma(dev, page)		(__arch_page_to_dma(dev, page))
-#define dma_to_virt(dev, addr)		(__arch_dma_to_virt(dev, addr))
-#define virt_to_dma(dev, addr)		(__arch_virt_to_dma(dev, addr))
-#endif
-
 /*
  * Optional coherency support.  Currently used only by selected
  * Intel XSC3-based systems.

arch/arm/include/asm/mtd-xip.h

@@ -10,8 +10,6 @@
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
- *
- * $Id: xip.h,v 1.2 2004/12/01 15:49:10 nico Exp $
  */
 
 #ifndef __ARM_MTD_XIP_H__

arch/arm/include/asm/processor.h

@@ -112,9 +112,9 @@ extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
 static inline void prefetch(const void *ptr)
 {
 	__asm__ __volatile__(
-		"pld\t%0"
+		"pld\t%a0"
 		:
-		: "o" (*(char *)ptr)
+		: "p" (ptr)
 		: "cc");
 }
 

arch/arm/include/asm/tlbflush.h

@@ -54,6 +54,7 @@
  *	  v4wbi - ARMv4 with write buffer with I TLB flush entry instruction
  *	  fr    - Feroceon (v4wbi with non-outer-cacheable page table walks)
  *	  v6wbi - ARMv6 with write buffer with I TLB flush entry instruction
+ *	  v7wbi - identical to v6wbi
  */
 #undef _TLB
 #undef MULTI_TLB
@@ -266,14 +267,16 @@ extern struct cpu_tlb_fns cpu_tlb;
 				 v4wbi_possible_flags | \
 				 fr_possible_flags | \
 				 v4wb_possible_flags | \
-				 v6wbi_possible_flags)
+				 v6wbi_possible_flags | \
+				 v7wbi_possible_flags)
 
 #define always_tlb_flags	(v3_always_flags & \
 				 v4_always_flags & \
 				 v4wbi_always_flags & \
 				 fr_always_flags & \
 				 v4wb_always_flags & \
-				 v6wbi_always_flags)
+				 v6wbi_always_flags & \
+				 v7wbi_always_flags)
 
 #define tlb_flag(f)	((always_tlb_flags & (f)) || (__tlb_flag & possible_tlb_flags & (f)))
 

arch/arm/include/asm/unistd.h

@@ -381,6 +381,12 @@
 #define __NR_fallocate			(__NR_SYSCALL_BASE+352)
 #define __NR_timerfd_settime		(__NR_SYSCALL_BASE+353)
 #define __NR_timerfd_gettime		(__NR_SYSCALL_BASE+354)
+#define __NR_signalfd4			(__NR_SYSCALL_BASE+355)
+#define __NR_eventfd2			(__NR_SYSCALL_BASE+356)
+#define __NR_epoll_create1		(__NR_SYSCALL_BASE+357)
+#define __NR_dup3			(__NR_SYSCALL_BASE+358)
+#define __NR_pipe2			(__NR_SYSCALL_BASE+359)
+#define __NR_inotify_init1		(__NR_SYSCALL_BASE+360)
 
 /*
  * The following SWIs are ARM private.

arch/arm/kernel/.gitignore

@@ -0,0 +1 @@
+vmlinux.lds

arch/arm/kernel/calls.S

@@ -262,10 +262,10 @@
 /* 250 */	CALL(sys_epoll_create)
 		CALL(ABI(sys_epoll_ctl, sys_oabi_epoll_ctl))
 		CALL(ABI(sys_epoll_wait, sys_oabi_epoll_wait))
-	 	CALL(sys_remap_file_pages)
+		CALL(sys_remap_file_pages)
 		CALL(sys_ni_syscall)	/* sys_set_thread_area */
 /* 255 */	CALL(sys_ni_syscall)	/* sys_get_thread_area */
- 		CALL(sys_set_tid_address)
+		CALL(sys_set_tid_address)
 		CALL(sys_timer_create)
 		CALL(sys_timer_settime)
 		CALL(sys_timer_gettime)
@@ -364,6 +364,12 @@
 		CALL(sys_fallocate)
 		CALL(sys_timerfd_settime)
 		CALL(sys_timerfd_gettime)
+/* 355 */	CALL(sys_signalfd4)
+		CALL(sys_eventfd2)
+		CALL(sys_epoll_create1)
+		CALL(sys_dup3)
+		CALL(sys_pipe2)
+/* 360 */	CALL(sys_inotify_init1)
 #ifndef syscalls_counted
 .equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls
 #define syscalls_counted

arch/arm/kernel/setup.c

@@ -81,6 +81,8 @@ EXPORT_SYMBOL(system_serial_high);
 unsigned int elf_hwcap;
 EXPORT_SYMBOL(elf_hwcap);
 
+unsigned long __initdata vmalloc_reserve = 128 << 20;
+
 
 #ifdef MULTI_CPU
 struct processor processor;
@@ -500,6 +502,17 @@ static void __init early_mem(char **p)
 }
 __early_param("mem=", early_mem);
 
+/*
+ * vmalloc=size forces the vmalloc area to be exactly 'size'
+ * bytes. This can be used to increase (or decrease) the vmalloc
+ * area - the default is 128m.
+ */
+static void __init early_vmalloc(char **arg)
+{
+	vmalloc_reserve = memparse(*arg, arg);
+}
+__early_param("vmalloc=", early_vmalloc);
+
 /*
  * Initial parsing of the command line.
  */

arch/arm/kernel/traps.c

@@ -288,14 +288,28 @@ void unregister_undef_hook(struct undef_hook *hook)
 	spin_unlock_irqrestore(&undef_lock, flags);
 }
 
+static int call_undef_hook(struct pt_regs *regs, unsigned int instr)
+{
+	struct undef_hook *hook;
+	unsigned long flags;
+	int (*fn)(struct pt_regs *regs, unsigned int instr) = NULL;
+
+	spin_lock_irqsave(&undef_lock, flags);
+	list_for_each_entry(hook, &undef_hook, node)
+		if ((instr & hook->instr_mask) == hook->instr_val &&
+		    (regs->ARM_cpsr & hook->cpsr_mask) == hook->cpsr_val)
+			fn = hook->fn;
+	spin_unlock_irqrestore(&undef_lock, flags);
+
+	return fn ? fn(regs, instr) : 1;
+}
+
 asmlinkage void __exception do_undefinstr(struct pt_regs *regs)
 {
 	unsigned int correction = thumb_mode(regs) ? 2 : 4;
 	unsigned int instr;
-	struct undef_hook *hook;
 	siginfo_t info;
 	void __user *pc;
-	unsigned long flags;
 
 	/*
 	 * According to the ARM ARM, PC is 2 or 4 bytes ahead,
@@ -325,17 +339,8 @@ asmlinkage void __exception do_undefinstr(struct pt_regs *regs)
 	}
 #endif
 
-	spin_lock_irqsave(&undef_lock, flags);
-	list_for_each_entry(hook, &undef_hook, node) {
-		if ((instr & hook->instr_mask) == hook->instr_val &&
-		    (regs->ARM_cpsr & hook->cpsr_mask) == hook->cpsr_val) {
-			if (hook->fn(regs, instr) == 0) {
-				spin_unlock_irqrestore(&undef_lock, flags);
-				return;
-			}
-		}
-	}
-	spin_unlock_irqrestore(&undef_lock, flags);
+	if (call_undef_hook(regs, instr) == 0)
+		return;
 
 #ifdef CONFIG_DEBUG_USER
 	if (user_debug & UDBG_UNDEFINED) {

arch/arm/mach-footbridge/cats-pci.c

@@ -18,6 +18,9 @@ static int irqmap_cats[] __initdata = { IRQ_PCI, IRQ_IN0, IRQ_IN1, IRQ_IN3 };
 
 static int __init cats_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 {
+	if (dev->irq >= 255)
+		return -1;	/* not a valid interrupt. */
+
 	if (dev->irq >= 128)
 		return dev->irq & 0x1f;
 

arch/arm/mach-integrator/cpu.c

@@ -3,8 +3,6 @@
  *
  *  Copyright (C) 2001-2002 Deep Blue Solutions Ltd.
  *
- *  $Id: cpu.c,v 1.6 2002/07/18 13:58:51 rmk Exp $
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.

arch/arm/mach-integrator/include/mach/platform.h

@@ -26,8 +26,6 @@
  * 	NOTE: This is a multi-hosted header file for use with uHAL and
  * 	      supported debuggers.
  *
- * 	$Id: platform.s,v 1.32 2000/02/18 10:51:39 asims Exp $
- *
  * ***********************************************************************/
 
 #ifndef __address_h

arch/arm/mach-kirkwood/common.c

@@ -15,15 +15,17 @@
 #include <linux/mbus.h>
 #include <linux/mv643xx_eth.h>
 #include <linux/ata_platform.h>
+#include <linux/spi/orion_spi.h>
 #include <asm/page.h>
 #include <asm/timex.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 #include <mach/kirkwood.h>
-#include <asm/plat-orion/cache-feroceon-l2.h>
-#include <asm/plat-orion/ehci-orion.h>
-#include <asm/plat-orion/orion_nand.h>
-#include <asm/plat-orion/time.h>
+#include <plat/cache-feroceon-l2.h>
+#include <plat/ehci-orion.h>
+#include <plat/mv_xor.h>
+#include <plat/orion_nand.h>
+#include <plat/time.h>
 #include "common.h"
 
 /*****************************************************************************
@@ -195,6 +197,37 @@ void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data)
 }
 
 
+/*****************************************************************************
+ * SPI
+ ****************************************************************************/
+static struct orion_spi_info kirkwood_spi_plat_data = {
+	.tclk		= KIRKWOOD_TCLK,
+};
+
+static struct resource kirkwood_spi_resources[] = {
+	{
+		.start	= SPI_PHYS_BASE,
+		.end	= SPI_PHYS_BASE + SZ_512 - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+};
+
+static struct platform_device kirkwood_spi = {
+	.name		= "orion_spi",
+	.id		= 0,
+	.resource	= kirkwood_spi_resources,
+	.dev		= {
+		.platform_data	= &kirkwood_spi_plat_data,
+	},
+	.num_resources	= ARRAY_SIZE(kirkwood_spi_resources),
+};
+
+void __init kirkwood_spi_init()
+{
+	platform_device_register(&kirkwood_spi);
+}
+
+
 /*****************************************************************************
  * UART0
  ****************************************************************************/
@@ -283,6 +316,212 @@ void __init kirkwood_uart1_init(void)
 }
 
 
+/*****************************************************************************
+ * XOR
+ ****************************************************************************/
+static struct mv_xor_platform_shared_data kirkwood_xor_shared_data = {
+	.dram		= &kirkwood_mbus_dram_info,
+};
+
+static u64 kirkwood_xor_dmamask = DMA_32BIT_MASK;
+
+
+/*****************************************************************************
+ * XOR0
+ ****************************************************************************/
+static struct resource kirkwood_xor0_shared_resources[] = {
+	{
+		.name	= "xor 0 low",
+		.start	= XOR0_PHYS_BASE,
+		.end	= XOR0_PHYS_BASE + 0xff,
+		.flags	= IORESOURCE_MEM,
+	}, {
+		.name	= "xor 0 high",
+		.start	= XOR0_HIGH_PHYS_BASE,
+		.end	= XOR0_HIGH_PHYS_BASE + 0xff,
+		.flags	= IORESOURCE_MEM,
+	},
+};
+
+static struct platform_device kirkwood_xor0_shared = {
+	.name		= MV_XOR_SHARED_NAME,
+	.id		= 0,
+	.dev		= {
+		.platform_data = &kirkwood_xor_shared_data,
+	},
+	.num_resources	= ARRAY_SIZE(kirkwood_xor0_shared_resources),
+	.resource	= kirkwood_xor0_shared_resources,
+};
+
+static struct resource kirkwood_xor00_resources[] = {
+	[0] = {
+		.start	= IRQ_KIRKWOOD_XOR_00,
+		.end	= IRQ_KIRKWOOD_XOR_00,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct mv_xor_platform_data kirkwood_xor00_data = {
+	.shared		= &kirkwood_xor0_shared,
+	.hw_id		= 0,
+	.pool_size	= PAGE_SIZE,
+};
+
+static struct platform_device kirkwood_xor00_channel = {
+	.name		= MV_XOR_NAME,
+	.id		= 0,
+	.num_resources	= ARRAY_SIZE(kirkwood_xor00_resources),
+	.resource	= kirkwood_xor00_resources,
+	.dev		= {
+		.dma_mask		= &kirkwood_xor_dmamask,
+		.coherent_dma_mask	= DMA_64BIT_MASK,
+		.platform_data		= (void *)&kirkwood_xor00_data,
+	},
+};
+
+static struct resource kirkwood_xor01_resources[] = {
+	[0] = {
+		.start	= IRQ_KIRKWOOD_XOR_01,
+		.end	= IRQ_KIRKWOOD_XOR_01,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct mv_xor_platform_data kirkwood_xor01_data = {
+	.shared		= &kirkwood_xor0_shared,
+	.hw_id		= 1,
+	.pool_size	= PAGE_SIZE,
+};
+
+static struct platform_device kirkwood_xor01_channel = {
+	.name		= MV_XOR_NAME,
+	.id		= 1,
+	.num_resources	= ARRAY_SIZE(kirkwood_xor01_resources),
+	.resource	= kirkwood_xor01_resources,
+	.dev		= {
+		.dma_mask		= &kirkwood_xor_dmamask,
+		.coherent_dma_mask	= DMA_64BIT_MASK,
+		.platform_data		= (void *)&kirkwood_xor01_data,
+	},
+};
+
+void __init kirkwood_xor0_init(void)
+{
+	platform_device_register(&kirkwood_xor0_shared);
+
+	/*
+	 * two engines can't do memset simultaneously, this limitation
+	 * satisfied by removing memset support from one of the engines.
+	 */
+	dma_cap_set(DMA_MEMCPY, kirkwood_xor00_data.cap_mask);
+	dma_cap_set(DMA_XOR, kirkwood_xor00_data.cap_mask);
+	platform_device_register(&kirkwood_xor00_channel);
+
+	dma_cap_set(DMA_MEMCPY, kirkwood_xor01_data.cap_mask);
+	dma_cap_set(DMA_MEMSET, kirkwood_xor01_data.cap_mask);
+	dma_cap_set(DMA_XOR, kirkwood_xor01_data.cap_mask);
+	platform_device_register(&kirkwood_xor01_channel);
+}
+
+
+/*****************************************************************************
+ * XOR1
+ ****************************************************************************/
+static struct resource kirkwood_xor1_shared_resources[] = {
+	{
+		.name	= "xor 1 low",
+		.start	= XOR1_PHYS_BASE,
+		.end	= XOR1_PHYS_BASE + 0xff,
+		.flags	= IORESOURCE_MEM,
+	}, {
+		.name	= "xor 1 high",
+		.start	= XOR1_HIGH_PHYS_BASE,
+		.end	= XOR1_HIGH_PHYS_BASE + 0xff,
+		.flags	= IORESOURCE_MEM,
+	},
+};
+
+static struct platform_device kirkwood_xor1_shared = {
+	.name		= MV_XOR_SHARED_NAME,
+	.id		= 1,
+	.dev		= {
+		.platform_data = &kirkwood_xor_shared_data,
+	},
+	.num_resources	= ARRAY_SIZE(kirkwood_xor1_shared_resources),
+	.resource	= kirkwood_xor1_shared_resources,
+};
+
+static struct resource kirkwood_xor10_resources[] = {
+	[0] = {
+		.start	= IRQ_KIRKWOOD_XOR_10,
+		.end	= IRQ_KIRKWOOD_XOR_10,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct mv_xor_platform_data kirkwood_xor10_data = {
+	.shared		= &kirkwood_xor1_shared,
+	.hw_id		= 0,
+	.pool_size	= PAGE_SIZE,
+};
+
+static struct platform_device kirkwood_xor10_channel = {
+	.name		= MV_XOR_NAME,
+	.id		= 2,
+	.num_resources	= ARRAY_SIZE(kirkwood_xor10_resources),
+	.resource	= kirkwood_xor10_resources,
+	.dev		= {
+		.dma_mask		= &kirkwood_xor_dmamask,
+		.coherent_dma_mask	= DMA_64BIT_MASK,
+		.platform_data		= (void *)&kirkwood_xor10_data,
+	},
+};
+
+static struct resource kirkwood_xor11_resources[] = {
+	[0] = {
+		.start	= IRQ_KIRKWOOD_XOR_11,
+		.end	= IRQ_KIRKWOOD_XOR_11,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct mv_xor_platform_data kirkwood_xor11_data = {
+	.shared		= &kirkwood_xor1_shared,
+	.hw_id		= 1,
+	.pool_size	= PAGE_SIZE,
+};
+
+static struct platform_device kirkwood_xor11_channel = {
+	.name		= MV_XOR_NAME,
+	.id		= 3,
+	.num_resources	= ARRAY_SIZE(kirkwood_xor11_resources),
+	.resource	= kirkwood_xor11_resources,
+	.dev		= {
+		.dma_mask		= &kirkwood_xor_dmamask,
+		.coherent_dma_mask	= DMA_64BIT_MASK,
+		.platform_data		= (void *)&kirkwood_xor11_data,
+	},
+};
+
+void __init kirkwood_xor1_init(void)
+{
+	platform_device_register(&kirkwood_xor1_shared);
+
+	/*
+	 * two engines can't do memset simultaneously, this limitation
+	 * satisfied by removing memset support from one of the engines.
+	 */
+	dma_cap_set(DMA_MEMCPY, kirkwood_xor10_data.cap_mask);
+	dma_cap_set(DMA_XOR, kirkwood_xor10_data.cap_mask);
+	platform_device_register(&kirkwood_xor10_channel);
+
+	dma_cap_set(DMA_MEMCPY, kirkwood_xor11_data.cap_mask);
+	dma_cap_set(DMA_MEMSET, kirkwood_xor11_data.cap_mask);
+	dma_cap_set(DMA_XOR, kirkwood_xor11_data.cap_mask);
+	platform_device_register(&kirkwood_xor11_channel);
+}
+
+
 /*****************************************************************************
  * Time handling
  ****************************************************************************/

arch/arm/mach-kirkwood/common.h

@@ -33,8 +33,11 @@ void kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data);
 void kirkwood_pcie_init(void);
 void kirkwood_rtc_init(void);
 void kirkwood_sata_init(struct mv_sata_platform_data *sata_data);
+void kirkwood_spi_init(void);
 void kirkwood_uart0_init(void);
 void kirkwood_uart1_init(void);
+void kirkwood_xor0_init(void);
+void kirkwood_xor1_init(void);
 
 extern struct sys_timer kirkwood_timer;
 

arch/arm/mach-kirkwood/include/mach/kirkwood.h

@@ -88,6 +88,15 @@
 
 #define USB_PHYS_BASE		(KIRKWOOD_REGS_PHYS_BASE | 0x50000)
 
+#define XOR0_PHYS_BASE		(KIRKWOOD_REGS_PHYS_BASE | 0x60800)
+#define XOR0_VIRT_BASE		(KIRKWOOD_REGS_VIRT_BASE | 0x60800)
+#define XOR1_PHYS_BASE		(KIRKWOOD_REGS_PHYS_BASE | 0x60900)
+#define XOR1_VIRT_BASE		(KIRKWOOD_REGS_VIRT_BASE | 0x60900)
+#define XOR0_HIGH_PHYS_BASE	(KIRKWOOD_REGS_PHYS_BASE | 0x60A00)
+#define XOR0_HIGH_VIRT_BASE	(KIRKWOOD_REGS_VIRT_BASE | 0x60A00)
+#define XOR1_HIGH_PHYS_BASE	(KIRKWOOD_REGS_PHYS_BASE | 0x60B00)
+#define XOR1_HIGH_VIRT_BASE	(KIRKWOOD_REGS_VIRT_BASE | 0x60B00)
+
 #define GE00_PHYS_BASE		(KIRKWOOD_REGS_PHYS_BASE | 0x70000)
 #define GE01_PHYS_BASE		(KIRKWOOD_REGS_PHYS_BASE | 0x74000)
 

arch/arm/mach-kirkwood/irq.c

@@ -12,7 +12,7 @@
 #include <linux/init.h>
 #include <linux/irq.h>
 #include <linux/io.h>
-#include <asm/plat-orion/irq.h>
+#include <plat/irq.h>
 #include "common.h"
 
 void __init kirkwood_init_irq(void)

arch/arm/mach-kirkwood/pcie.c

@@ -12,7 +12,7 @@
 #include <linux/pci.h>
 #include <linux/mbus.h>
 #include <asm/mach/pci.h>
-#include <asm/plat-orion/pcie.h>
+#include <plat/pcie.h>
 #include "common.h"
 
 

arch/arm/mach-kirkwood/rd88f6192-nas-setup.c

@@ -18,6 +18,9 @@
 #include <linux/timer.h>
 #include <linux/ata_platform.h>
 #include <linux/mv643xx_eth.h>
+#include <linux/spi/flash.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/orion_spi.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
@@ -34,6 +37,21 @@ static struct mv_sata_platform_data rd88f6192_sata_data = {
 	.n_ports	= 2,
 };
 
+static const struct flash_platform_data rd88F6192_spi_slave_data = {
+	.type		= "m25p128",
+};
+
+static struct spi_board_info __initdata rd88F6192_spi_slave_info[] = {
+	{
+		.modalias	= "m25p80",
+		.platform_data	= &rd88F6192_spi_slave_data,
+		.irq		= -1,
+		.max_speed_hz	= 20000000,
+		.bus_num	= 0,
+		.chip_select	= 0,
+	},
+};
+
 static void __init rd88f6192_init(void)
 {
 	/*
@@ -45,7 +63,12 @@ static void __init rd88f6192_init(void)
 	kirkwood_ge00_init(&rd88f6192_ge00_data);
 	kirkwood_rtc_init();
 	kirkwood_sata_init(&rd88f6192_sata_data);
+	spi_register_board_info(rd88F6192_spi_slave_info,
+				ARRAY_SIZE(rd88F6192_spi_slave_info));
+	kirkwood_spi_init();
 	kirkwood_uart0_init();
+	kirkwood_xor0_init();
+	kirkwood_xor1_init();
 }
 
 static int __init rd88f6192_pci_init(void)

arch/arm/mach-kirkwood/rd88f6281-setup.c

@@ -23,7 +23,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
 #include <mach/kirkwood.h>
-#include <asm/plat-orion/orion_nand.h>
+#include <plat/orion_nand.h>
 #include "common.h"
 
 static struct mtd_partition rd88f6281_nand_parts[] = {

arch/arm/mach-lh7a40x/include/mach/ssp.h

@@ -1,5 +1,4 @@
 /* ssp.h
-     $Id$
 
    written by Marc Singer
    6 Dec 2004

arch/arm/mach-lh7a40x/lcd-panel.h

@@ -1,5 +1,4 @@
 /* lcd-panel.h
-     $Id$
 
    written by Marc Singer
    18 Jul 2005

arch/arm/mach-loki/common.c

@@ -19,8 +19,8 @@
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 #include <mach/loki.h>
-#include <asm/plat-orion/orion_nand.h>
-#include <asm/plat-orion/time.h>
+#include <plat/orion_nand.h>
+#include <plat/time.h>
 #include "common.h"
 
 /*****************************************************************************

arch/arm/mach-loki/irq.c

@@ -12,7 +12,7 @@
 #include <linux/init.h>
 #include <linux/irq.h>
 #include <asm/io.h>
-#include <asm/plat-orion/irq.h>
+#include <plat/irq.h>
 #include "common.h"
 
 void __init loki_init_irq(void)

arch/arm/mach-mv78xx0/common.c

@@ -18,10 +18,10 @@
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 #include <mach/mv78xx0.h>
-#include <asm/plat-orion/cache-feroceon-l2.h>
-#include <asm/plat-orion/ehci-orion.h>
-#include <asm/plat-orion/orion_nand.h>
-#include <asm/plat-orion/time.h>
+#include <plat/cache-feroceon-l2.h>
+#include <plat/ehci-orion.h>
+#include <plat/orion_nand.h>
+#include <plat/time.h>
 #include "common.h"
 
 

arch/arm/mach-mv78xx0/irq.c

@@ -12,7 +12,7 @@
 #include <linux/init.h>
 #include <linux/pci.h>
 #include <mach/mv78xx0.h>
-#include <asm/plat-orion/irq.h>
+#include <plat/irq.h>
 #include "common.h"
 
 void __init mv78xx0_init_irq(void)

arch/arm/mach-mv78xx0/pcie.c

@@ -12,7 +12,7 @@
 #include <linux/pci.h>
 #include <linux/mbus.h>
 #include <asm/mach/pci.h>
-#include <asm/plat-orion/pcie.h>
+#include <plat/pcie.h>
 #include "common.h"
 
 struct pcie_port {

arch/arm/mach-orion5x/common.c

@@ -26,9 +26,10 @@
 #include <asm/mach/time.h>
 #include <mach/hardware.h>
 #include <mach/orion5x.h>
-#include <asm/plat-orion/ehci-orion.h>
-#include <asm/plat-orion/orion_nand.h>
-#include <asm/plat-orion/time.h>
+#include <plat/ehci-orion.h>
+#include <plat/mv_xor.h>
+#include <plat/orion_nand.h>
+#include <plat/time.h>
 #include "common.h"
 
 /*****************************************************************************
@@ -354,6 +355,103 @@ void __init orion5x_uart1_init(void)
 }
 
 
+/*****************************************************************************
+ * XOR engine
+ ****************************************************************************/
+static struct resource orion5x_xor_shared_resources[] = {
+	{
+		.name	= "xor low",
+		.start	= ORION5X_XOR_PHYS_BASE,
+		.end	= ORION5X_XOR_PHYS_BASE + 0xff,
+		.flags	= IORESOURCE_MEM,
+	}, {
+		.name	= "xor high",
+		.start	= ORION5X_XOR_PHYS_BASE + 0x200,
+		.end	= ORION5X_XOR_PHYS_BASE + 0x2ff,
+		.flags	= IORESOURCE_MEM,
+	},
+};
+
+static struct platform_device orion5x_xor_shared = {
+	.name		= MV_XOR_SHARED_NAME,
+	.id		= 0,
+	.num_resources	= ARRAY_SIZE(orion5x_xor_shared_resources),
+	.resource	= orion5x_xor_shared_resources,
+};
+
+static u64 orion5x_xor_dmamask = DMA_32BIT_MASK;
+
+static struct resource orion5x_xor0_resources[] = {
+	[0] = {
+		.start	= IRQ_ORION5X_XOR0,
+		.end	= IRQ_ORION5X_XOR0,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct mv_xor_platform_data orion5x_xor0_data = {
+	.shared		= &orion5x_xor_shared,
+	.hw_id		= 0,
+	.pool_size	= PAGE_SIZE,
+};
+
+static struct platform_device orion5x_xor0_channel = {
+	.name		= MV_XOR_NAME,
+	.id		= 0,
+	.num_resources	= ARRAY_SIZE(orion5x_xor0_resources),
+	.resource	= orion5x_xor0_resources,
+	.dev		= {
+		.dma_mask		= &orion5x_xor_dmamask,
+		.coherent_dma_mask	= DMA_64BIT_MASK,
+		.platform_data		= (void *)&orion5x_xor0_data,
+	},
+};
+
+static struct resource orion5x_xor1_resources[] = {
+	[0] = {
+		.start	= IRQ_ORION5X_XOR1,
+		.end	= IRQ_ORION5X_XOR1,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct mv_xor_platform_data orion5x_xor1_data = {
+	.shared		= &orion5x_xor_shared,
+	.hw_id		= 1,
+	.pool_size	= PAGE_SIZE,
+};
+
+static struct platform_device orion5x_xor1_channel = {
+	.name		= MV_XOR_NAME,
+	.id		= 1,
+	.num_resources	= ARRAY_SIZE(orion5x_xor1_resources),
+	.resource	= orion5x_xor1_resources,
+	.dev		= {
+		.dma_mask		= &orion5x_xor_dmamask,
+		.coherent_dma_mask	= DMA_64BIT_MASK,
+		.platform_data		= (void *)&orion5x_xor1_data,
+	},
+};
+
+void __init orion5x_xor_init(void)
+{
+	platform_device_register(&orion5x_xor_shared);
+
+	/*
+	 * two engines can't do memset simultaneously, this limitation
+	 * satisfied by removing memset support from one of the engines.
+	 */
+	dma_cap_set(DMA_MEMCPY, orion5x_xor0_data.cap_mask);
+	dma_cap_set(DMA_XOR, orion5x_xor0_data.cap_mask);
+	platform_device_register(&orion5x_xor0_channel);
+
+	dma_cap_set(DMA_MEMCPY, orion5x_xor1_data.cap_mask);
+	dma_cap_set(DMA_MEMSET, orion5x_xor1_data.cap_mask);
+	dma_cap_set(DMA_XOR, orion5x_xor1_data.cap_mask);
+	platform_device_register(&orion5x_xor1_channel);
+}
+
+
 /*****************************************************************************
  * Time handling
  ****************************************************************************/
@@ -382,6 +480,8 @@ static void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name)
 			*dev_name = "MV88F5281-D2";
 		} else if (*rev == MV88F5281_REV_D1) {
 			*dev_name = "MV88F5281-D1";
+		} else if (*rev == MV88F5281_REV_D0) {
+			*dev_name = "MV88F5281-D0";
 		} else {
 			*dev_name = "MV88F5281-Rev-Unsupported";
 		}
@@ -416,6 +516,15 @@ void __init orion5x_init(void)
 	 * Setup Orion address map
 	 */
 	orion5x_setup_cpu_mbus_bridge();
+
+	/*
+	 * Don't issue "Wait for Interrupt" instruction if we are
+	 * running on D0 5281 silicon.
+	 */
+	if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) {
+		printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n");
+		disable_hlt();
+	}
 }
 
 /*

arch/arm/mach-orion5x/common.h

@@ -32,6 +32,7 @@ void orion5x_i2c_init(void);
 void orion5x_sata_init(struct mv_sata_platform_data *sata_data);
 void orion5x_uart0_init(void);
 void orion5x_uart1_init(void);
+void orion5x_xor_init(void);
 
 /*
  * PCIe/PCI functions.

arch/arm/mach-orion5x/db88f5281-setup.c

@@ -25,7 +25,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
 #include <mach/orion5x.h>
-#include <asm/plat-orion/orion_nand.h>
+#include <plat/orion_nand.h>
 #include "common.h"
 #include "mpp.h"
 

arch/arm/mach-orion5x/include/mach/orion5x.h

@@ -73,6 +73,7 @@
 #define MV88F5182_REV_A2	2
 /* Orion-2 (88F5281) */
 #define MV88F5281_DEV_ID	0x5281
+#define MV88F5281_REV_D0	4
 #define MV88F5281_REV_D1	5
 #define MV88F5281_REV_D2	6
 
@@ -105,6 +106,10 @@
 #define ORION5X_USB0_VIRT_BASE		(ORION5X_REGS_VIRT_BASE | 0x50000)
 #define ORION5X_USB0_REG(x)		(ORION5X_USB0_VIRT_BASE | (x))
 
+#define ORION5X_XOR_PHYS_BASE		(ORION5X_REGS_PHYS_BASE | 0x60900)
+#define ORION5X_XOR_VIRT_BASE		(ORION5X_REGS_VIRT_BASE | 0x60900)
+#define ORION5X_XOR_REG(x)		(ORION5X_XOR_VIRT_BASE | (x))
+
 #define ORION5X_ETH_PHYS_BASE		(ORION5X_REGS_PHYS_BASE | 0x70000)
 #define ORION5X_ETH_VIRT_BASE		(ORION5X_REGS_VIRT_BASE | 0x70000)
 #define ORION5X_ETH_REG(x)		(ORION5X_ETH_VIRT_BASE | (x))

arch/arm/mach-orion5x/irq.c

@@ -16,7 +16,7 @@
 #include <asm/gpio.h>
 #include <asm/io.h>
 #include <mach/orion5x.h>
-#include <asm/plat-orion/irq.h>
+#include <plat/irq.h>
 #include "common.h"
 
 /*****************************************************************************

arch/arm/mach-orion5x/kurobox_pro-setup.c

@@ -25,7 +25,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
 #include <mach/orion5x.h>
-#include <asm/plat-orion/orion_nand.h>
+#include <plat/orion_nand.h>
 #include "common.h"
 #include "mpp.h"
 
@@ -356,6 +356,7 @@ static void __init kurobox_pro_init(void)
 	orion5x_sata_init(&kurobox_pro_sata_data);
 	orion5x_uart0_init();
 	orion5x_uart1_init();
+	orion5x_xor_init();
 
 	orion5x_setup_dev_boot_win(KUROBOX_PRO_NOR_BOOT_BASE,
 				   KUROBOX_PRO_NOR_BOOT_SIZE);

arch/arm/mach-orion5x/mss2-setup.c

@@ -239,6 +239,7 @@ static void __init mss2_init(void)
 	orion5x_i2c_init();
 	orion5x_sata_init(&mss2_sata_data);
 	orion5x_uart0_init();
+	orion5x_xor_init();
 
 	orion5x_setup_dev_boot_win(MSS2_NOR_BOOT_BASE, MSS2_NOR_BOOT_SIZE);
 	platform_device_register(&mss2_nor_flash);

arch/arm/mach-orion5x/mv2120-setup.c

@@ -203,6 +203,7 @@ static void __init mv2120_init(void)
 	orion5x_i2c_init();
 	orion5x_sata_init(&mv2120_sata_data);
 	orion5x_uart0_init();
+	orion5x_xor_init();
 
 	orion5x_setup_dev_boot_win(MV2120_NOR_BOOT_BASE, MV2120_NOR_BOOT_SIZE);
 	platform_device_register(&mv2120_nor_flash);

arch/arm/mach-orion5x/pci.c

@@ -14,7 +14,7 @@
 #include <linux/pci.h>
 #include <linux/mbus.h>
 #include <asm/mach/pci.h>
-#include <asm/plat-orion/pcie.h>
+#include <plat/pcie.h>
 #include "common.h"
 
 /*****************************************************************************

arch/arm/mach-orion5x/rd88f5182-setup.c

@@ -292,6 +292,7 @@ static void __init rd88f5182_init(void)
 	orion5x_i2c_init();
 	orion5x_sata_init(&rd88f5182_sata_data);
 	orion5x_uart0_init();
+	orion5x_xor_init();
 
 	orion5x_setup_dev_boot_win(RD88F5182_NOR_BOOT_BASE,
 				   RD88F5182_NOR_BOOT_SIZE);

arch/arm/mach-orion5x/ts209-setup.c

@@ -207,12 +207,12 @@ static struct i2c_board_info __initdata qnap_ts209_i2c_rtc = {
 
 static struct gpio_keys_button qnap_ts209_buttons[] = {
 	{
-		.code		= KEY_RESTART,
+		.code		= KEY_COPY,
 		.gpio		= QNAP_TS209_GPIO_KEY_MEDIA,
 		.desc		= "USB Copy Button",
 		.active_low	= 1,
 	}, {
-		.code		= KEY_POWER,
+		.code		= KEY_RESTART,
 		.gpio		= QNAP_TS209_GPIO_KEY_RESET,
 		.desc		= "Reset Button",
 		.active_low	= 1,
@@ -296,6 +296,7 @@ static void __init qnap_ts209_init(void)
 	orion5x_i2c_init();
 	orion5x_sata_init(&qnap_ts209_sata_data);
 	orion5x_uart0_init();
+	orion5x_xor_init();
 
 	orion5x_setup_dev_boot_win(QNAP_TS209_NOR_BOOT_BASE,
 				   QNAP_TS209_NOR_BOOT_SIZE);

arch/arm/mach-orion5x/ts409-setup.c

@@ -3,6 +3,9 @@
  *
  * Maintainer: Sylver Bruneau <sylver.bruneau@gmail.com>
  *
+ * Copyright (C) 2008  Sylver Bruneau <sylver.bruneau@gmail.com>
+ * Copyright (C) 2008  Martin Michlmayr <tbm@cyrius.com>
+ *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
  * as published by the Free Software Foundation; either version
@@ -16,6 +19,7 @@
 #include <linux/irq.h>
 #include <linux/mtd/physmap.h>
 #include <linux/mv643xx_eth.h>
+#include <linux/leds.h>
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
 #include <linux/i2c.h>
@@ -162,16 +166,59 @@ static struct i2c_board_info __initdata qnap_ts409_i2c_rtc = {
 	I2C_BOARD_INFO("s35390a", 0x30),
 };
 
+/*****************************************************************************
+ * LEDs attached to GPIO
+ ****************************************************************************/
+
+static struct gpio_led ts409_led_pins[] = {
+	{
+		.name		= "ts409:red:sata1",
+		.gpio		= 4,
+		.active_low	= 1,
+	}, {
+		.name		= "ts409:red:sata2",
+		.gpio		= 5,
+		.active_low	= 1,
+	}, {
+		.name		= "ts409:red:sata3",
+		.gpio		= 6,
+		.active_low	= 1,
+	}, {
+		.name		= "ts409:red:sata4",
+		.gpio		= 7,
+		.active_low	= 1,
+	},
+};
+
+static struct gpio_led_platform_data ts409_led_data = {
+	.leds		= ts409_led_pins,
+	.num_leds	= ARRAY_SIZE(ts409_led_pins),
+};
+
+static struct platform_device ts409_leds = {
+	.name	= "leds-gpio",
+	.id	= -1,
+	.dev	= {
+		.platform_data	= &ts409_led_data,
+	},
+};
+
 /****************************************************************************
  * GPIO Attached Keys
  *     Power button is attached to the PIC microcontroller
  ****************************************************************************/
 
+#define QNAP_TS409_GPIO_KEY_RESET	14
 #define QNAP_TS409_GPIO_KEY_MEDIA	15
 
 static struct gpio_keys_button qnap_ts409_buttons[] = {
 	{
 		.code		= KEY_RESTART,
+		.gpio		= QNAP_TS409_GPIO_KEY_RESET,
+		.desc		= "Reset Button",
+		.active_low	= 1,
+	}, {
+		.code		= KEY_COPY,
 		.gpio		= QNAP_TS409_GPIO_KEY_MEDIA,
 		.desc		= "USB Copy Button",
 		.active_low	= 1,
@@ -255,6 +302,7 @@ static void __init qnap_ts409_init(void)
 	if (qnap_ts409_i2c_rtc.irq == 0)
 		pr_warning("qnap_ts409_init: failed to get RTC IRQ\n");
 	i2c_register_board_info(0, &qnap_ts409_i2c_rtc, 1);
+	platform_device_register(&ts409_leds);
 
 	/* register tsx09 specific power-off method */
 	pm_power_off = qnap_tsx09_power_off;

arch/arm/mach-orion5x/ts78xx-setup.c

@@ -256,6 +256,7 @@ static void __init ts78xx_init(void)
 	orion5x_sata_init(&ts78xx_sata_data);
 	orion5x_uart0_init();
 	orion5x_uart1_init();
+	orion5x_xor_init();
 
 	orion5x_setup_dev_boot_win(TS78XX_NOR_BOOT_BASE,
 				   TS78XX_NOR_BOOT_SIZE);

arch/arm/mach-pxa/include/mach/mtd-xip.h

@@ -10,8 +10,6 @@
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
- *
- * $Id: xip.h,v 1.2 2004/12/01 15:49:10 nico Exp $
  */
 
 #ifndef __ARCH_PXA_MTD_XIP_H__

arch/arm/mach-pxa/include/mach/poodle.h

@@ -70,6 +70,12 @@
 #define POODLE_SCOOP_IO_DIR	( POODLE_SCOOP_VPEN | POODLE_SCOOP_HS_OUT )
 #define POODLE_SCOOP_IO_OUT	( 0 )
 
+#define POODLE_LOCOMO_GPIO_AMP_ON      LOCOMO_GPIO(8)
+#define POODLE_LOCOMO_GPIO_MUTE_L      LOCOMO_GPIO(10)
+#define POODLE_LOCOMO_GPIO_MUTE_R      LOCOMO_GPIO(11)
+#define POODLE_LOCOMO_GPIO_232VCC_ON   LOCOMO_GPIO(12)
+#define POODLE_LOCOMO_GPIO_JK_B        LOCOMO_GPIO(13)
+
 extern struct platform_device poodle_locomo_device;
 
 #endif /* __ASM_ARCH_POODLE_H  */

arch/arm/mach-pxa/include/mach/pxafb.h

@@ -28,6 +28,7 @@
  * bits 10-17 : for AC Bias Pin Frequency
  * bit     18 : for output enable polarity
  * bit     19 : for pixel clock edge
+ * bit     20 : for output pixel format when base is RGBT16
  */
 #define LCD_CONN_TYPE(_x)	((_x) & 0x0f)
 #define LCD_CONN_WIDTH(_x)	(((_x) >> 4) & 0x1f)
@@ -53,10 +54,11 @@
 #define LCD_SMART_PANEL_18BPP	((18 << 4) | LCD_TYPE_SMART_PANEL)
 
 #define LCD_AC_BIAS_FREQ(x)	(((x) & 0xff) << 10)
-#define LCD_BIAS_ACTIVE_HIGH	(0 << 17)
-#define LCD_BIAS_ACTIVE_LOW	(1 << 17)
-#define LCD_PCLK_EDGE_RISE	(0 << 18)
-#define LCD_PCLK_EDGE_FALL	(1 << 18)
+#define LCD_BIAS_ACTIVE_HIGH	(0 << 18)
+#define LCD_BIAS_ACTIVE_LOW	(1 << 18)
+#define LCD_PCLK_EDGE_RISE	(0 << 19)
+#define LCD_PCLK_EDGE_FALL	(1 << 19)
+#define LCD_ALTERNATE_MAPPING	(1 << 20)
 
 /*
  * This structure describes the machine which we are running on.

arch/arm/mach-s3c2410/include/mach/regs-clock.h

@@ -11,7 +11,7 @@
 */
 
 #ifndef __ASM_ARM_REGS_CLOCK
-#define __ASM_ARM_REGS_CLOCK "$Id: clock.h,v 1.4 2003/04/30 14:50:51 ben Exp $"
+#define __ASM_ARM_REGS_CLOCK
 
 #define S3C2410_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR)
 

arch/arm/mach-s3c2410/include/mach/regs-gpio.h

@@ -12,7 +12,7 @@
 
 
 #ifndef __ASM_ARCH_REGS_GPIO_H
-#define __ASM_ARCH_REGS_GPIO_H "$Id: gpio.h,v 1.5 2003/05/19 12:51:08 ben Exp $"
+#define __ASM_ARCH_REGS_GPIO_H
 
 #define S3C2410_GPIONO(bank,offset) ((bank) + (offset))
 

arch/arm/mach-s3c2410/include/mach/regs-irq.h

@@ -10,7 +10,7 @@
 
 
 #ifndef ___ASM_ARCH_REGS_IRQ_H
-#define ___ASM_ARCH_REGS_IRQ_H "$Id: irq.h,v 1.3 2003/03/25 21:29:06 ben Exp $"
+#define ___ASM_ARCH_REGS_IRQ_H
 
 /* interrupt controller */
 

arch/arm/mach-s3c2410/include/mach/regs-lcd.h

@@ -10,7 +10,7 @@
 
 
 #ifndef ___ASM_ARCH_REGS_LCD_H
-#define ___ASM_ARCH_REGS_LCD_H "$Id: lcd.h,v 1.3 2003/06/26 13:25:06 ben Exp $"
+#define ___ASM_ARCH_REGS_LCD_H
 
 #define S3C2410_LCDREG(x)	(x)
 

arch/arm/mach-s3c2410/include/mach/regs-mem.h

@@ -11,7 +11,7 @@
 */
 
 #ifndef __ASM_ARM_MEMREGS_H
-#define __ASM_ARM_MEMREGS_H "$Id: regs.h,v 1.8 2003/05/01 15:55:41 ben Exp $"
+#define __ASM_ARM_MEMREGS_H
 
 #ifndef S3C2410_MEMREG
 #define S3C2410_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))

arch/arm/mach-s3c2410/mach-bast.c

@@ -562,7 +562,7 @@ static struct platform_device *bast_devices[] __initdata = {
 	&bast_sio,
 };
 
-static struct clk *bast_clocks[] = {
+static struct clk *bast_clocks[] __initdata = {
 	&s3c24xx_dclk0,
 	&s3c24xx_dclk1,
 	&s3c24xx_clkout0,

arch/arm/mach-s3c2410/mach-smdk2410.c

@@ -5,7 +5,6 @@
  * Copyright (C) 2004 by FS Forth-Systeme GmbH
  * All rights reserved.
  *
- * $Id: mach-smdk2410.c,v 1.1 2004/05/11 14:15:38 mpietrek Exp $
  * @Author: Jonas Dietsche
  *
  * This program is free software; you can redistribute it and/or

arch/arm/mach-s3c2410/mach-vr1000.c

@@ -344,7 +344,7 @@ static struct platform_device *vr1000_devices[] __initdata = {
 	&vr1000_led3,
 };
 
-static struct clk *vr1000_clocks[] = {
+static struct clk *vr1000_clocks[] __initdata = {
 	&s3c24xx_dclk0,
 	&s3c24xx_dclk1,
 	&s3c24xx_clkout0,

arch/arm/mach-s3c2412/mach-jive.c

@@ -26,9 +26,6 @@
 
 #include <linux/spi/spi.h>
 
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>

arch/arm/mach-s3c2440/mach-anubis.c

@@ -414,7 +414,7 @@ static struct platform_device *anubis_devices[] __initdata = {
 	&anubis_device_sm501,
 };
 
-static struct clk *anubis_clocks[] = {
+static struct clk *anubis_clocks[] __initdata = {
 	&s3c24xx_dclk0,
 	&s3c24xx_dclk1,
 	&s3c24xx_clkout0,

arch/arm/mach-s3c2440/mach-osiris.c

@@ -341,7 +341,7 @@ static struct platform_device *osiris_devices[] __initdata = {
 	&osiris_pcmcia,
 };
 
-static struct clk *osiris_clocks[] = {
+static struct clk *osiris_clocks[] __initdata = {
 	&s3c24xx_dclk0,
 	&s3c24xx_dclk1,
 	&s3c24xx_clkout0,

arch/arm/mach-sa1100/cpu-sa1110.c

@@ -3,8 +3,6 @@
  *
  *  Copyright (C) 2001 Russell King
  *
- *  $Id: cpu-sa1110.c,v 1.9 2002/07/06 16:53:18 rmk Exp $
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.

arch/arm/mach-sa1100/include/mach/mtd-xip.h

@@ -10,8 +10,6 @@
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
- *
- * $Id: xip.h,v 1.2 2004/12/01 15:49:10 nico Exp $
  */
 
 #ifndef __ARCH_SA1100_MTD_XIP_H__

arch/arm/mm/cache-feroceon-l2.c

@@ -14,7 +14,7 @@
 
 #include <linux/init.h>
 #include <asm/cacheflush.h>
-#include <asm/plat-orion/cache-feroceon-l2.h>
+#include <plat/cache-feroceon-l2.h>
 
 
 /*

arch/arm/mm/mmu.c

@@ -568,6 +568,55 @@ void __init iotable_init(struct map_desc *io_desc, int nr)
 		create_mapping(io_desc + i);
 }
 
+static int __init check_membank_valid(struct membank *mb)
+{
+	/*
+	 * Check whether this memory region has non-zero size.
+	 */
+	if (mb->size == 0)
+		return 0;
+
+	/*
+	 * Check whether this memory region would entirely overlap
+	 * the vmalloc area.
+	 */
+	if (phys_to_virt(mb->start) >= VMALLOC_MIN) {
+		printk(KERN_NOTICE "Ignoring RAM at %.8lx-%.8lx "
+			"(vmalloc region overlap).\n",
+			mb->start, mb->start + mb->size - 1);
+		return 0;
+	}
+
+	/*
+	 * Check whether this memory region would partially overlap
+	 * the vmalloc area.
+	 */
+	if (phys_to_virt(mb->start + mb->size) < phys_to_virt(mb->start) ||
+	    phys_to_virt(mb->start + mb->size) > VMALLOC_MIN) {
+		unsigned long newsize = VMALLOC_MIN - phys_to_virt(mb->start);
+
+		printk(KERN_NOTICE "Truncating RAM at %.8lx-%.8lx "
+			"to -%.8lx (vmalloc region overlap).\n",
+			mb->start, mb->start + mb->size - 1,
+			mb->start + newsize - 1);
+		mb->size = newsize;
+	}
+
+	return 1;
+}
+
+static void __init sanity_check_meminfo(struct meminfo *mi)
+{
+	int i;
+	int j;
+
+	for (i = 0, j = 0; i < mi->nr_banks; i++) {
+		if (check_membank_valid(&mi->bank[i]))
+			mi->bank[j++] = mi->bank[i];
+	}
+	mi->nr_banks = j;
+}
+
 static inline void prepare_page_table(struct meminfo *mi)
 {
 	unsigned long addr;
@@ -753,6 +802,7 @@ void __init paging_init(struct meminfo *mi, struct machine_desc *mdesc)
 	void *zero_page;
 
 	build_mem_type_table();
+	sanity_check_meminfo(mi);
 	prepare_page_table(mi);
 	bootmem_init(mi);
 	devicemaps_init(mdesc);

arch/arm/mm/proc-arm940.S

@@ -15,6 +15,7 @@
 #include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 #include <asm/ptrace.h>
+#include "proc-macros.S"
 
 /* ARM940T has a 4KB DCache comprising 256 lines of 4 words */
 #define CACHE_DLINESIZE	16

arch/arm/mm/proc-arm946.S

@@ -17,6 +17,7 @@
 #include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 #include <asm/ptrace.h>
+#include "proc-macros.S"
 
 /*
  * ARM946E-S is synthesizable to have 0KB to 1MB sized D-Cache,

arch/arm/plat-omap/include/mach/memory.h

@@ -76,13 +76,14 @@
 					(dma_addr_t)virt_to_lbus(page_address(page)) : \
 					(dma_addr_t)__virt_to_bus(page_address(page));})
 
-#define __arch_dma_to_virt(dev, addr)	({is_lbus_device(dev) ? \
-					lbus_to_virt(addr) : \
-					__bus_to_virt(addr);})
-
-#define __arch_virt_to_dma(dev, addr)	({is_lbus_device(dev) ? \
-					virt_to_lbus(addr) : \
-					__virt_to_bus(addr);})
+#define __arch_dma_to_virt(dev, addr)	({ (void *) (is_lbus_device(dev) ? \
+						lbus_to_virt(addr) : \
+						__bus_to_virt(addr)); })
+
+#define __arch_virt_to_dma(dev, addr)	({ unsigned long __addr = (unsigned long)(addr); \
+					   (dma_addr_t) (is_lbus_device(dev) ? \
+						virt_to_lbus(__addr) : \
+						__virt_to_bus(__addr)); })
 
 #endif	/* CONFIG_ARCH_OMAP15XX */
 

include/asm-arm/plat-orion/cache-feroceon-l2.h → arch/arm/plat-orion/include/plat/cache-feroceon-l2.h

@@ -1,5 +1,5 @@
 /*
- * include/asm-arm/plat-orion/cache-feroceon-l2.h
+ * arch/arm/plat-orion/include/plat/cache-feroceon-l2.h
  *
  * Copyright (C) 2008 Marvell Semiconductor
  *

include/asm-arm/plat-orion/ehci-orion.h → arch/arm/plat-orion/include/plat/ehci-orion.h

@@ -1,13 +1,13 @@
 /*
- * include/asm-arm/plat-orion/ehci-orion.h
+ * arch/arm/plat-orion/include/plat/ehci-orion.h
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2.  This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
 
-#ifndef __ASM_PLAT_ORION_EHCI_ORION_H
-#define __ASM_PLAT_ORION_EHCI_ORION_H
+#ifndef __PLAT_EHCI_ORION_H
+#define __PLAT_EHCI_ORION_H
 
 #include <linux/mbus.h>
 

include/asm-arm/plat-orion/irq.h → arch/arm/plat-orion/include/plat/irq.h

@@ -1,5 +1,5 @@
 /*
- * include/asm-arm/plat-orion/irq.h
+ * arch/arm/plat-orion/include/plat/irq.h
  *
  * Marvell Orion SoC IRQ handling.
  *
@@ -8,8 +8,8 @@
  * warranty of any kind, whether express or implied.
  */
 
-#ifndef __ASM_PLAT_ORION_IRQ_H
-#define __ASM_PLAT_ORION_IRQ_H
+#ifndef __PLAT_IRQ_H
+#define __PLAT_IRQ_H
 
 void orion_irq_init(unsigned int irq_start, void __iomem *maskaddr);
 

include/asm-arm/plat-orion/mv_xor.h → arch/arm/plat-orion/include/plat/mv_xor.h

@@ -1,9 +1,11 @@
 /*
+ * arch/arm/plat-orion/include/plat/mv_xor.h
+ *
  * Marvell XOR platform device data definition file.
  */
 
-#ifndef __ASM_PLAT_ORION_MV_XOR_H
-#define __ASM_PLAT_ORION_MV_XOR_H
+#ifndef __PLAT_MV_XOR_H
+#define __PLAT_MV_XOR_H
 
 #include <linux/dmaengine.h>
 #include <linux/mbus.h>

include/asm-arm/plat-orion/orion_nand.h → arch/arm/plat-orion/include/plat/orion_nand.h

@@ -1,13 +1,13 @@
 /*
- * include/asm-arm/plat-orion/orion_nand.h
+ * arch/arm/plat-orion/include/plat/orion_nand.h
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2.  This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
 
-#ifndef __ASM_PLAT_ORION_ORION_NAND_H
-#define __ASM_PLAT_ORION_ORION_NAND_H
+#ifndef __PLAT_ORION_NAND_H
+#define __PLAT_ORION_NAND_H
 
 /*
  * Device bus NAND private data

include/asm-arm/plat-orion/pcie.h → arch/arm/plat-orion/include/plat/pcie.h

@@ -1,5 +1,5 @@
 /*
- * include/asm-arm/plat-orion/pcie.h
+ * arch/arm/plat-orion/include/plat/pcie.h
  *
  * Marvell Orion SoC PCIe handling.
  *
@@ -8,8 +8,8 @@
  * warranty of any kind, whether express or implied.
  */
 
-#ifndef __ASM_PLAT_ORION_PCIE_H
-#define __ASM_PLAT_ORION_PCIE_H
+#ifndef __PLAT_PCIE_H
+#define __PLAT_PCIE_H
 
 u32 orion_pcie_dev_id(void __iomem *base);
 u32 orion_pcie_rev(void __iomem *base);

include/asm-arm/plat-orion/time.h → arch/arm/plat-orion/include/plat/time.h

@@ -1,5 +1,5 @@
 /*
- * include/asm-arm/plat-orion/time.h
+ * arch/arm/plat-orion/include/plat/time.h
  *
  * Marvell Orion SoC time handling.
  *
@@ -8,8 +8,8 @@
  * warranty of any kind, whether express or implied.
  */
 
-#ifndef __ASM_PLAT_ORION_TIME_H
-#define __ASM_PLAT_ORION_TIME_H
+#ifndef __PLAT_TIME_H
+#define __PLAT_TIME_H
 
 void orion_time_init(unsigned int irq, unsigned int tclk);
 

arch/arm/plat-orion/irq.c

@@ -12,7 +12,7 @@
 #include <linux/init.h>
 #include <linux/irq.h>
 #include <linux/io.h>
-#include <asm/plat-orion/irq.h>
+#include <plat/irq.h>
 
 static void orion_irq_mask(u32 irq)
 {

arch/arm/plat-orion/pcie.c

@@ -12,7 +12,7 @@
 #include <linux/pci.h>
 #include <linux/mbus.h>
 #include <asm/mach/pci.h>
-#include <asm/plat-orion/pcie.h>
+#include <plat/pcie.h>
 
 /*
  * PCIe unit register offsets.

arch/arm/plat-s3c24xx/cpu.c

@@ -169,9 +169,7 @@ static struct map_desc s3c_iodesc[] __initdata = {
 	IODESC_ENT(UART)
 };
 
-
-static struct cpu_table *
-s3c_lookup_cpu(unsigned long idcode)
+static struct cpu_table * __init s3c_lookup_cpu(unsigned long idcode)
 {
 	struct cpu_table *tab;
 	int count;

arch/arm/tools/mach-types

@@ -12,7 +12,7 @@
 #
 #   http://www.arm.linux.org.uk/developer/machines/?action=new
 #
-# Last update: Sun Jul 13 12:04:05 2008
+# Last update: Wed Aug 13 21:56:02 2008
 #
 # machine_is_xxx	CONFIG_xxxx		MACH_TYPE_xxx		number
 #
@@ -843,7 +843,7 @@ borzoi			MACH_BORZOI		BORZOI			831
 gecko			MACH_GECKO		GECKO			832
 ds101			MACH_DS101		DS101			833
 omap_palmtt2		MACH_OMAP_PALMTT2	OMAP_PALMTT2		834
-xscale_palmld		MACH_XSCALE_PALMLD	XSCALE_PALMLD		835
+palmld			MACH_PALMLD		PALMLD			835
 cc9c			MACH_CC9C		CC9C			836
 sbc1670			MACH_SBC1670		SBC1670			837
 ixdp28x5		MACH_IXDP28X5		IXDP28X5		838
@@ -852,7 +852,7 @@ ml696k			MACH_ML696K		ML696K			840
 arcom_zeus		MACH_ARCOM_ZEUS		ARCOM_ZEUS		841
 osiris			MACH_OSIRIS		OSIRIS			842
 maestro			MACH_MAESTRO		MAESTRO			843
-tunge2			MACH_TUNGE2		TUNGE2			844
+palmte2			MACH_PALMTE2		PALMTE2			844
 ixbbm			MACH_IXBBM		IXBBM			845
 mx27ads			MACH_MX27ADS		MX27ADS			846
 ax8004			MACH_AX8004		AX8004			847
@@ -916,7 +916,7 @@ nxdb500			MACH_NXDB500		NXDB500			905
 apf9328			MACH_APF9328		APF9328			906
 omap_wipoq		MACH_OMAP_WIPOQ		OMAP_WIPOQ		907
 omap_twip		MACH_OMAP_TWIP		OMAP_TWIP		908
-palmtreo650		MACH_PALMTREO650	PALMTREO650		909
+palmt650		MACH_PALMT650		PALMT650		909
 acumen			MACH_ACUMEN		ACUMEN			910
 xp100			MACH_XP100		XP100			911
 fs2410			MACH_FS2410		FS2410			912
@@ -1096,7 +1096,7 @@ atc6			MACH_ATC6		ATC6			1086
 multmdw			MACH_MULTMDW		MULTMDW			1087
 mba2440			MACH_MBA2440		MBA2440			1088
 ecsd			MACH_ECSD		ECSD			1089
-zire31			MACH_ZIRE31		ZIRE31			1090
+palmz31			MACH_PALMZ31		PALMZ31			1090
 fsg			MACH_FSG		FSG			1091
 razor101		MACH_RAZOR101		RAZOR101		1092
 opera_tdm		MACH_OPERA_TDM		OPERA_TDM		1093
@@ -1810,7 +1810,7 @@ kriss_sensor		MACH_KRISS_SENSOR	KRISS_SENSOR		1819
 pilz_pmi5		MACH_PILZ_PMI5		PILZ_PMI5		1820
 jade			MACH_JADE		JADE			1821
 ks8695_softplc		MACH_KS8695_SOFTPLC	KS8695_SOFTPLC		1822
-gprisc4			MACH_GPRISC4		GPRISC4			1823
+gprisc3			MACH_GPRISC4		GPRISC4			1823
 stamp9260		MACH_STAMP9260		STAMP9260		1824
 smdk6430		MACH_SMDK6430		SMDK6430		1825
 smdkc100		MACH_SMDKC100		SMDKC100		1826
@@ -1820,3 +1820,44 @@ deister_eyecam		MACH_DEISTER_EYECAM	DEISTER_EYECAM		1829
 at91sam9m10ek		MACH_AT91SAM9M10EK	AT91SAM9M10EK		1830
 linkstation_produo	MACH_LINKSTATION_PRODUO	LINKSTATION_PRODUO	1831
 hit_b0			MACH_HIT_B0		HIT_B0			1832
+adx_rmu			MACH_ADX_RMU		ADX_RMU			1833
+xg_cpe_main		MACH_XG_CPE_MAIN	XG_CPE_MAIN		1834
+edb9407a		MACH_EDB9407A		EDB9407A		1835
+dtb9608			MACH_DTB9608		DTB9608			1836
+em104v1			MACH_EM104V1		EM104V1			1837
+demo			MACH_DEMO		DEMO			1838
+logi9260		MACH_LOGI9260		LOGI9260		1839
+mx31_exm32		MACH_MX31_EXM32		MX31_EXM32		1840
+usb_a9g20		MACH_USB_A9G20		USB_A9G20		1841
+picproje2008		MACH_PICPROJE2008	PICPROJE2008		1842
+cs_e9315		MACH_CS_E9315		CS_E9315		1843
+qil_a9g20		MACH_QIL_A9G20		QIL_A9G20		1844
+sha_pon020		MACH_SHA_PON020		SHA_PON020		1845
+nad			MACH_NAD		NAD			1846
+sbc35_a9260		MACH_SBC35_A9260	SBC35_A9260		1847
+sbc35_a9g20		MACH_SBC35_A9G20	SBC35_A9G20		1848
+davinci_beginning	MACH_DAVINCI_BEGINNING	DAVINCI_BEGINNING	1849
+uwc			MACH_UWC		UWC			1850
+mxlads			MACH_MXLADS		MXLADS			1851
+htcnike			MACH_HTCNIKE		HTCNIKE			1852
+deister_pxa270		MACH_DEISTER_PXA270	DEISTER_PXA270		1853
+cme9210js		MACH_CME9210JS		CME9210JS		1854
+cc9p9360		MACH_CC9P9360		CC9P9360		1855
+mocha			MACH_MOCHA		MOCHA			1856
+wapd170ag		MACH_WAPD170AG		WAPD170AG		1857
+linkstation_mini	MACH_LINKSTATION_MINI	LINKSTATION_MINI	1858
+afeb9260		MACH_AFEB9260		AFEB9260		1859
+w90x900			MACH_W90X900		W90X900			1860
+w90x700			MACH_W90X700		W90X700			1861
+kt300ip			MACH_KT300IP		KT300IP			1862
+kt300ip_g20		MACH_KT300IP_G20	KT300IP_G20		1863
+srcm			MACH_SRCM		SRCM			1864
+wlnx_9260		MACH_WLNX_9260		WLNX_9260		1865
+openmoko_gta03		MACH_OPENMOKO_GTA03	OPENMOKO_GTA03		1866
+osprey2			MACH_OSPREY2		OSPREY2			1867
+kbio9260		MACH_KBIO9260		KBIO9260		1868
+ginza			MACH_GINZA		GINZA			1869
+a636n			MACH_A636N		A636N			1870
+imx27ipcam		MACH_IMX27IPCAM		IMX27IPCAM		1871
+nenoc			MACH_NEMOC		NEMOC			1872
+geneva			MACH_GENEVA		GENEVA			1873

drivers/dma/mv_xor.c

@@ -25,7 +25,7 @@
 #include <linux/interrupt.h>
 #include <linux/platform_device.h>
 #include <linux/memory.h>
-#include <asm/plat-orion/mv_xor.h>
+#include <plat/mv_xor.h>
 #include "mv_xor.h"
 
 static void mv_xor_issue_pending(struct dma_chan *chan);

drivers/mtd/nand/orion_nand.c

@@ -19,7 +19,7 @@
 #include <asm/io.h>
 #include <asm/sizes.h>
 #include <mach/hardware.h>
-#include <asm/plat-orion/orion_nand.h>
+#include <plat/orion_nand.h>
 
 #ifdef CONFIG_MTD_CMDLINE_PARTS
 static const char *part_probes[] = { "cmdlinepart", NULL };

drivers/pcmcia/pxa2xx_palmtx.c

@@ -23,12 +23,57 @@
 
 static int palmtx_pcmcia_hw_init(struct soc_pcmcia_socket *skt)
 {
-	skt->irq = IRQ_GPIO(GPIO_NR_PALMTX_PCMCIA_READY);
+	int ret;
+
+	ret = gpio_request(GPIO_NR_PALMTX_PCMCIA_POWER1, "PCMCIA PWR1");
+	if (ret)
+		goto err1;
+	ret = gpio_direction_output(GPIO_NR_PALMTX_PCMCIA_POWER1, 0);
+	if (ret)
+		goto err2;
+
+	ret = gpio_request(GPIO_NR_PALMTX_PCMCIA_POWER2, "PCMCIA PWR2");
+	if (ret)
+		goto err2;
+	ret = gpio_direction_output(GPIO_NR_PALMTX_PCMCIA_POWER2, 0);
+	if (ret)
+		goto err3;
+
+	ret = gpio_request(GPIO_NR_PALMTX_PCMCIA_RESET, "PCMCIA RST");
+	if (ret)
+		goto err3;
+	ret = gpio_direction_output(GPIO_NR_PALMTX_PCMCIA_RESET, 1);
+	if (ret)
+		goto err4;
+
+	ret = gpio_request(GPIO_NR_PALMTX_PCMCIA_READY, "PCMCIA RDY");
+	if (ret)
+		goto err4;
+	ret = gpio_direction_input(GPIO_NR_PALMTX_PCMCIA_READY);
+	if (ret)
+		goto err5;
+
+	skt->irq = gpio_to_irq(GPIO_NR_PALMTX_PCMCIA_READY);
 	return 0;
+
+err5:
+	gpio_free(GPIO_NR_PALMTX_PCMCIA_READY);
+err4:
+	gpio_free(GPIO_NR_PALMTX_PCMCIA_RESET);
+err3:
+	gpio_free(GPIO_NR_PALMTX_PCMCIA_POWER2);
+err2:
+	gpio_free(GPIO_NR_PALMTX_PCMCIA_POWER1);
+err1:
+	return ret;
 }
 
 static void palmtx_pcmcia_hw_shutdown(struct soc_pcmcia_socket *skt)
 {
+	gpio_free(GPIO_NR_PALMTX_PCMCIA_READY);
+	gpio_free(GPIO_NR_PALMTX_PCMCIA_RESET);
+	gpio_free(GPIO_NR_PALMTX_PCMCIA_POWER2);
+	gpio_free(GPIO_NR_PALMTX_PCMCIA_POWER1);
 }
 
 static void palmtx_pcmcia_socket_state(struct soc_pcmcia_socket *skt,
@@ -109,7 +154,7 @@ static void __exit palmtx_pcmcia_exit(void)
 	platform_device_unregister(palmtx_pcmcia_device);
 }
 
-fs_initcall(palmtx_pcmcia_init);
+module_init(palmtx_pcmcia_init);
 module_exit(palmtx_pcmcia_exit);
 
 MODULE_AUTHOR("Marek Vasut <marek.vasut@gmail.com>");

drivers/serial/Kconfig

@@ -449,6 +449,7 @@ config SERIAL_CLPS711X_CONSOLE
 config SERIAL_SAMSUNG
 	tristate "Samsung SoC serial support"
 	depends on ARM && PLAT_S3C24XX
+	select SERIAL_CORE
 	help
 	  Support for the on-chip UARTs on the Samsung S3C24XX series CPUs,
 	  providing /dev/ttySAC0, 1 and 2 (note, some machines may not

drivers/usb/host/ehci-orion.c

@@ -12,7 +12,7 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/mbus.h>
-#include <asm/plat-orion/ehci-orion.h>
+#include <plat/ehci-orion.h>
 
 #define rdl(off)	__raw_readl(hcd->regs + (off))
 #define wrl(off, val)	__raw_writel((val), hcd->regs + (off))

drivers/video/pxafb.c

@@ -1031,7 +1031,9 @@ static void pxafb_setup_gpio(struct pxafb_info *fbi)
 	pxa_gpio_mode(GPIO74_LCD_FCLK_MD);
 	pxa_gpio_mode(GPIO75_LCD_LCLK_MD);
 	pxa_gpio_mode(GPIO76_LCD_PCLK_MD);
-	pxa_gpio_mode(GPIO77_LCD_ACBIAS_MD);
+
+	if ((lccr0 & LCCR0_PAS) == 0)
+		pxa_gpio_mode(GPIO77_LCD_ACBIAS_MD);
 }
 
 static void pxafb_enable_controller(struct pxafb_info *fbi)
@@ -1400,6 +1402,8 @@ static void pxafb_decode_mach_info(struct pxafb_info *fbi,
 	if (lcd_conn == LCD_MONO_STN_8BPP)
 		fbi->lccr0 |= LCCR0_DPD;
 
+	fbi->lccr0 |= (lcd_conn & LCD_ALTERNATE_MAPPING) ? LCCR0_LDDALT : 0;
+
 	fbi->lccr3 = LCCR3_Acb((inf->lcd_conn >> 10) & 0xff);
 	fbi->lccr3 |= (lcd_conn & LCD_BIAS_ACTIVE_LOW) ? LCCR3_OEP : 0;
 	fbi->lccr3 |= (lcd_conn & LCD_PCLK_EDGE_FALL)  ? LCCR3_PCP : 0;
@@ -1673,53 +1677,63 @@ MODULE_PARM_DESC(options, "LCD parameters (see Documentation/fb/pxafb.txt)");
 #define pxafb_setup_options()		(0)
 #endif
 
-static int __devinit pxafb_probe(struct platform_device *dev)
-{
-	struct pxafb_info *fbi;
-	struct pxafb_mach_info *inf;
-	struct resource *r;
-	int irq, ret;
-
-	dev_dbg(&dev->dev, "pxafb_probe\n");
-
-	inf = dev->dev.platform_data;
-	ret = -ENOMEM;
-	fbi = NULL;
-	if (!inf)
-		goto failed;
-
-	ret = pxafb_parse_options(&dev->dev, g_options);
-	if (ret < 0)
-		goto failed;
-
 #ifdef DEBUG_VAR
-	/* Check for various illegal bit-combinations. Currently only
-	 * a warning is given. */
+/* Check for various illegal bit-combinations. Currently only
+ * a warning is given. */
+static void __devinit pxafb_check_options(struct device *dev,
+					  struct pxafb_mach_info *inf)
+{
+	if (inf->lcd_conn)
+		return;
 
 	if (inf->lccr0 & LCCR0_INVALID_CONFIG_MASK)
-		dev_warn(&dev->dev, "machine LCCR0 setting contains "
+		dev_warn(dev, "machine LCCR0 setting contains "
 				"illegal bits: %08x\n",
 			inf->lccr0 & LCCR0_INVALID_CONFIG_MASK);
 	if (inf->lccr3 & LCCR3_INVALID_CONFIG_MASK)
-		dev_warn(&dev->dev, "machine LCCR3 setting contains "
+		dev_warn(dev, "machine LCCR3 setting contains "
 				"illegal bits: %08x\n",
 			inf->lccr3 & LCCR3_INVALID_CONFIG_MASK);
 	if (inf->lccr0 & LCCR0_DPD &&
 	    ((inf->lccr0 & LCCR0_PAS) != LCCR0_Pas ||
 	     (inf->lccr0 & LCCR0_SDS) != LCCR0_Sngl ||
 	     (inf->lccr0 & LCCR0_CMS) != LCCR0_Mono))
-		dev_warn(&dev->dev, "Double Pixel Data (DPD) mode is "
+		dev_warn(dev, "Double Pixel Data (DPD) mode is "
 				"only valid in passive mono"
 				" single panel mode\n");
 	if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Act &&
 	    (inf->lccr0 & LCCR0_SDS) == LCCR0_Dual)
-		dev_warn(&dev->dev, "Dual panel only valid in passive mode\n");
+		dev_warn(dev, "Dual panel only valid in passive mode\n");
 	if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Pas &&
 	     (inf->modes->upper_margin || inf->modes->lower_margin))
-		dev_warn(&dev->dev, "Upper and lower margins must be 0 in "
+		dev_warn(dev, "Upper and lower margins must be 0 in "
 				"passive mode\n");
+}
+#else
+#define pxafb_check_options(...)	do {} while (0)
 #endif
 
+static int __devinit pxafb_probe(struct platform_device *dev)
+{
+	struct pxafb_info *fbi;
+	struct pxafb_mach_info *inf;
+	struct resource *r;
+	int irq, ret;
+
+	dev_dbg(&dev->dev, "pxafb_probe\n");
+
+	inf = dev->dev.platform_data;
+	ret = -ENOMEM;
+	fbi = NULL;
+	if (!inf)
+		goto failed;
+
+	ret = pxafb_parse_options(&dev->dev, g_options);
+	if (ret < 0)
+		goto failed;
+
+	pxafb_check_options(&dev->dev, inf);
+
 	dev_dbg(&dev->dev, "got a %dx%dx%d LCD\n",
 			inf->modes->xres,
 			inf->modes->yres,

drivers/watchdog/s3c2410_wdt.c

@@ -157,8 +157,6 @@ static void s3c2410wdt_start(void)
 	writel(wdt_count, wdt_base + S3C2410_WTCNT);
 	writel(wtcon, wdt_base + S3C2410_WTCON);
 	spin_unlock(&wdt_lock);
-
-	return 0;
 }
 
 static int s3c2410wdt_set_heartbeat(int timeout)

include/asm-arm/plat-s3c/regs-nand.h

@@ -11,7 +11,7 @@
 */
 
 #ifndef __ASM_ARM_REGS_NAND
-#define __ASM_ARM_REGS_NAND "$Id: nand.h,v 1.3 2003/12/09 11:36:29 ben Exp $"
+#define __ASM_ARM_REGS_NAND
 
 
 #define S3C2410_NFREG(x) (x)

include/asm-arm/plat-s3c/regs-timer.h

@@ -12,7 +12,7 @@
 
 
 #ifndef __ASM_ARCH_REGS_TIMER_H
-#define __ASM_ARCH_REGS_TIMER_H "$Id: timer.h,v 1.4 2003/05/06 19:30:50 ben Exp $"
+#define __ASM_ARCH_REGS_TIMER_H
 
 #define S3C_TIMERREG(x) (S3C_VA_TIMER + (x))
 #define S3C_TIMERREG2(tmr,reg) S3C_TIMERREG((reg)+0x0c+((tmr)*0x0c))

include/asm-arm/plat-s3c/regs-watchdog.h

@@ -12,7 +12,7 @@
 
 
 #ifndef __ASM_ARCH_REGS_WATCHDOG_H
-#define __ASM_ARCH_REGS_WATCHDOG_H "$Id: watchdog.h,v 1.2 2003/04/29 13:31:09 ben Exp $"
+#define __ASM_ARCH_REGS_WATCHDOG_H
 
 #define S3C_WDOGREG(x) ((x) + S3C_VA_WATCHDOG)
 

include/asm-arm/plat-s3c24xx/s3c2410.h

@@ -21,11 +21,11 @@ extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 
 extern void s3c2410_init_clocks(int xtal);
 
-extern  int s3c2410_baseclk_add(void);
-
 #else
 #define s3c2410_init_clocks NULL
 #define s3c2410_init_uarts NULL
 #define s3c2410_map_io NULL
 #define s3c2410_init NULL
 #endif
+
+extern int s3c2410_baseclk_add(void);