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@@ -239,11 +239,13 @@ static void SA5_intr_mask(ctlr_info_t *h, unsigned long val)
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{ /* Turn interrupts on */
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h->interrupts_enabled = 1;
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writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
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+ (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
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} else /* Turn them off */
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{
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h->interrupts_enabled = 0;
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writel( SA5_INTR_OFF,
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h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
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+ (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
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}
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}
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/*
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@@ -257,11 +259,13 @@ static void SA5B_intr_mask(ctlr_info_t *h, unsigned long val)
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{ /* Turn interrupts on */
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h->interrupts_enabled = 1;
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writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
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+ (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
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} else /* Turn them off */
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{
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h->interrupts_enabled = 0;
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writel( SA5B_INTR_OFF,
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h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
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+ (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
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}
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}
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@@ -271,10 +275,12 @@ static void SA5_performant_intr_mask(ctlr_info_t *h, unsigned long val)
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if (val) { /* turn on interrupts */
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h->interrupts_enabled = 1;
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writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
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+ (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
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} else {
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h->interrupts_enabled = 0;
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writel(SA5_PERF_INTR_OFF,
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h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
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+ (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
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}
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}
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