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@@ -238,19 +238,6 @@ enum dsi_vc_source {
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DSI_VC_SOURCE_VP,
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};
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-enum dsi_lane {
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- DSI_CLK_P = 1 << 0,
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- DSI_CLK_N = 1 << 1,
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- DSI_DATA1_P = 1 << 2,
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- DSI_DATA1_N = 1 << 3,
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- DSI_DATA2_P = 1 << 4,
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- DSI_DATA2_N = 1 << 5,
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- DSI_DATA3_P = 1 << 6,
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- DSI_DATA3_N = 1 << 7,
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- DSI_DATA4_P = 1 << 8,
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- DSI_DATA4_N = 1 << 9,
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-};
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-
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struct dsi_update_region {
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u16 x, y, w, h;
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struct omap_dss_device *device;
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@@ -2290,49 +2277,28 @@ static void dsi_cio_timings(struct platform_device *dsidev)
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dsi_write_reg(dsidev, DSI_DSIPHY_CFG2, r);
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}
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+/* lane masks have lane 0 at lsb. mask_p for positive lines, n for negative */
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static void dsi_cio_enable_lane_override(struct omap_dss_device *dssdev,
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- enum dsi_lane lanes)
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+ unsigned mask_p, unsigned mask_n)
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{
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struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
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struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
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- int clk_lane = dssdev->phy.dsi.clk_lane;
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- int data1_lane = dssdev->phy.dsi.data1_lane;
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- int data2_lane = dssdev->phy.dsi.data2_lane;
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- int data3_lane = dssdev->phy.dsi.data3_lane;
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- int data4_lane = dssdev->phy.dsi.data4_lane;
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- int clk_pol = dssdev->phy.dsi.clk_pol;
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- int data1_pol = dssdev->phy.dsi.data1_pol;
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- int data2_pol = dssdev->phy.dsi.data2_pol;
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- int data3_pol = dssdev->phy.dsi.data3_pol;
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- int data4_pol = dssdev->phy.dsi.data4_pol;
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-
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- u32 l = 0;
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+ int i;
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+ u32 l;
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u8 lptxscp_start = dsi->num_lanes_supported == 3 ? 22 : 26;
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- if (lanes & DSI_CLK_P)
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- l |= 1 << ((clk_lane - 1) * 2 + (clk_pol ? 0 : 1));
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- if (lanes & DSI_CLK_N)
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- l |= 1 << ((clk_lane - 1) * 2 + (clk_pol ? 1 : 0));
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-
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- if (lanes & DSI_DATA1_P)
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- l |= 1 << ((data1_lane - 1) * 2 + (data1_pol ? 0 : 1));
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- if (lanes & DSI_DATA1_N)
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- l |= 1 << ((data1_lane - 1) * 2 + (data1_pol ? 1 : 0));
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-
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- if (lanes & DSI_DATA2_P)
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- l |= 1 << ((data2_lane - 1) * 2 + (data2_pol ? 0 : 1));
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- if (lanes & DSI_DATA2_N)
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- l |= 1 << ((data2_lane - 1) * 2 + (data2_pol ? 1 : 0));
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-
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- if (lanes & DSI_DATA3_P)
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- l |= 1 << ((data3_lane - 1) * 2 + (data3_pol ? 0 : 1));
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- if (lanes & DSI_DATA3_N)
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- l |= 1 << ((data3_lane - 1) * 2 + (data3_pol ? 1 : 0));
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-
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- if (lanes & DSI_DATA4_P)
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- l |= 1 << ((data4_lane - 1) * 2 + (data4_pol ? 0 : 1));
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- if (lanes & DSI_DATA4_N)
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- l |= 1 << ((data4_lane - 1) * 2 + (data4_pol ? 1 : 0));
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+ l = 0;
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+
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+ for (i = 0; i < dsi->num_lanes_supported; ++i) {
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+ unsigned p = dsi->lanes[i].polarity;
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+
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+ if (mask_p & (1 << i))
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+ l |= 1 << (i * 2 + (p ? 0 : 1));
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+
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+ if (mask_n & (1 << i))
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+ l |= 1 << (i * 2 + (p ? 1 : 0));
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+ }
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+
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/*
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* Bits in REGLPTXSCPDAT4TO0DXDY:
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* 17: DY0 18: DX0
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@@ -2432,7 +2398,6 @@ static int dsi_cio_init(struct omap_dss_device *dssdev)
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struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
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struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
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int r;
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- int num_lanes_used = dsi_get_num_lanes_used(dssdev);
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u32 l;
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DSSDBGF();
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@@ -2467,7 +2432,8 @@ static int dsi_cio_init(struct omap_dss_device *dssdev)
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dsi_write_reg(dsidev, DSI_TIMING1, l);
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if (dsi->ulps_enabled) {
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- u32 lane_mask = DSI_CLK_P | DSI_DATA1_P | DSI_DATA2_P;
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+ unsigned mask_p;
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+ int i;
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DSSDBG("manual ulps exit\n");
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@@ -2476,16 +2442,19 @@ static int dsi_cio_init(struct omap_dss_device *dssdev)
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* ULPS exit sequence, as after reset the DSS HW thinks
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* that we are not in ULPS mode, and refuses to send the
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* sequence. So we need to send the ULPS exit sequence
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- * manually.
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+ * manually by setting positive lines high and negative lines
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+ * low for 1ms.
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*/
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- if (num_lanes_used > 3)
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- lane_mask |= DSI_DATA3_P;
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+ mask_p = 0;
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- if (num_lanes_used > 4)
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- lane_mask |= DSI_DATA4_P;
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+ for (i = 0; i < dsi->num_lanes_supported; ++i) {
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+ if (dsi->lanes[i].function == DSI_LANE_UNUSED)
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+ continue;
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+ mask_p |= 1 << i;
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+ }
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- dsi_cio_enable_lane_override(dssdev, lane_mask);
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+ dsi_cio_enable_lane_override(dssdev, mask_p, 0);
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}
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r = dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ON);
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