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@@ -124,13 +124,13 @@ static void XGINew_SetMemoryClock(struct xgi_hw_device_info *HwDeviceExtension,
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xgifb_reg_set(pVBInfo->P3c4,
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0x2E,
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- pVBInfo->ECLKData[pVBInfo->ram_type].SR2E);
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+ XGI340_ECLKData[pVBInfo->ram_type].SR2E);
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xgifb_reg_set(pVBInfo->P3c4,
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0x2F,
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- pVBInfo->ECLKData[pVBInfo->ram_type].SR2F);
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+ XGI340_ECLKData[pVBInfo->ram_type].SR2F);
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xgifb_reg_set(pVBInfo->P3c4,
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0x30,
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- pVBInfo->ECLKData[pVBInfo->ram_type].SR30);
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+ XGI340_ECLKData[pVBInfo->ram_type].SR30);
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/* When XG42 ECLK = MCLK = 207MHz, Set SR32 D[1:0] = 10b */
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/* Modify SR32 value, when MCLK=207MHZ, ELCK=250MHz,
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@@ -138,10 +138,10 @@ static void XGINew_SetMemoryClock(struct xgi_hw_device_info *HwDeviceExtension,
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if (HwDeviceExtension->jChipType == XG42) {
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if ((pVBInfo->MCLKData[pVBInfo->ram_type].SR28 == 0x1C) &&
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(pVBInfo->MCLKData[pVBInfo->ram_type].SR29 == 0x01) &&
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- (((pVBInfo->ECLKData[pVBInfo->ram_type].SR2E == 0x1C) &&
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- (pVBInfo->ECLKData[pVBInfo->ram_type].SR2F == 0x01)) ||
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- ((pVBInfo->ECLKData[pVBInfo->ram_type].SR2E == 0x22) &&
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- (pVBInfo->ECLKData[pVBInfo->ram_type].SR2F == 0x01))))
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+ (((XGI340_ECLKData[pVBInfo->ram_type].SR2E == 0x1C) &&
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+ (XGI340_ECLKData[pVBInfo->ram_type].SR2F == 0x01)) ||
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+ ((XGI340_ECLKData[pVBInfo->ram_type].SR2E == 0x22) &&
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+ (XGI340_ECLKData[pVBInfo->ram_type].SR2F == 0x01))))
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xgifb_reg_set(pVBInfo->P3c4,
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0x32,
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((unsigned char) xgifb_reg_get(
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