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@@ -61,6 +61,8 @@
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/* global iommu list, set NULL for ignored DMAR units */
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static struct intel_iommu **g_iommus;
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+static int rwbf_quirk;
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+
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/*
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* 0: Present
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* 1-11: Reserved
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@@ -785,7 +787,7 @@ static void iommu_flush_write_buffer(struct intel_iommu *iommu)
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u32 val;
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unsigned long flag;
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- if (!cap_rwbf(iommu->cap))
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+ if (!rwbf_quirk && !cap_rwbf(iommu->cap))
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return;
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val = iommu->gcmd | DMA_GCMD_WBF;
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@@ -3137,3 +3139,15 @@ static struct iommu_ops intel_iommu_ops = {
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.unmap = intel_iommu_unmap_range,
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.iova_to_phys = intel_iommu_iova_to_phys,
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};
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+
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+static void __devinit quirk_iommu_rwbf(struct pci_dev *dev)
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+{
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+ /*
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+ * Mobile 4 Series Chipset neglects to set RWBF capability,
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+ * but needs it:
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+ */
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+ printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n");
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+ rwbf_quirk = 1;
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+}
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+
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+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);
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