Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc

* 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc: (202 commits)
  [POWERPC] Fix compile breakage for 64-bit UP configs
  [POWERPC] Define copy_siginfo_from_user32
  [POWERPC] Add compat handler for PTRACE_GETSIGINFO
  [POWERPC] i2c: Fix build breakage introduced by OF helpers
  [POWERPC] Optimize fls64() on 64-bit processors
  [POWERPC] irqtrace support for 64-bit powerpc
  [POWERPC] Stacktrace support for lockdep
  [POWERPC] Move stackframe definitions to common header
  [POWERPC] Fix device-tree locking vs. interrupts
  [POWERPC] Make pci_bus_to_host()'s struct pci_bus * argument const
  [POWERPC] Remove unused __max_memory variable
  [POWERPC] Simplify xics direct/lpar irq_host setup
  [POWERPC] Use pseries_setup_i8259_cascade() in pseries_mpic_init_IRQ()
  [POWERPC] Turn xics_setup_8259_cascade() into a generic pseries_setup_i8259_cascade()
  [POWERPC] Move xics_setup_8259_cascade() into platforms/pseries/setup.c
  [POWERPC] Use asm-generic/bitops/find.h in bitops.h
  [POWERPC] 83xx: mpc8315 - fix USB UTMI Host setup
  [POWERPC] 85xx: Fix the size of qe muram for MPC8568E
  [POWERPC] 86xx: mpc86xx_hpcn - Temporarily accept old dts node identifier.
  [POWERPC] 86xx: mark functions static, other minor cleanups
  ...

Documentation/kernel-parameters.txt

@@ -954,6 +954,8 @@ and is between 256 and 4096 characters. It is defined in the file
 
 	l2cr=		[PPC]
 
+	l3cr=		[PPC]
+
 	lapic		[X86-32,APIC] Enable the local APIC even if BIOS
 			disabled it.
 

Documentation/powerpc/booting-without-of.txt

@@ -59,12 +59,39 @@ Table of Contents
       p) Freescale Synchronous Serial Interface
 	  q) USB EHCI controllers
 
-  VII - Specifying interrupt information for devices
+  VII - Marvell Discovery mv64[345]6x System Controller chips
+    1) The /system-controller node
+    2) Child nodes of /system-controller
+      a) Marvell Discovery MDIO bus
+      b) Marvell Discovery ethernet controller
+      c) Marvell Discovery PHY nodes
+      d) Marvell Discovery SDMA nodes
+      e) Marvell Discovery BRG nodes
+      f) Marvell Discovery CUNIT nodes
+      g) Marvell Discovery MPSCROUTING nodes
+      h) Marvell Discovery MPSCINTR nodes
+      i) Marvell Discovery MPSC nodes
+      j) Marvell Discovery Watch Dog Timer nodes
+      k) Marvell Discovery I2C nodes
+      l) Marvell Discovery PIC (Programmable Interrupt Controller) nodes
+      m) Marvell Discovery MPP (Multipurpose Pins) multiplexing nodes
+      n) Marvell Discovery GPP (General Purpose Pins) nodes
+      o) Marvell Discovery PCI host bridge node
+      p) Marvell Discovery CPU Error nodes
+      q) Marvell Discovery SRAM Controller nodes
+      r) Marvell Discovery PCI Error Handler nodes
+      s) Marvell Discovery Memory Controller nodes
+
+  VIII - Specifying interrupt information for devices
     1) interrupts property
     2) interrupt-parent property
     3) OpenPIC Interrupt Controllers
     4) ISA Interrupt Controllers
 
+  VIII - Specifying GPIO information for devices
+    1) gpios property
+    2) gpio-controller nodes
+
   Appendix A - Sample SOC node for MPC8540
 
 
@@ -1269,10 +1296,6 @@ platforms are moved over to use the flattened-device-tree model.
 
   Recommended properties:
 
-    - linux,network-index : This is the intended "index" of this
-      network device.  This is used by the bootwrapper to interpret
-      MAC addresses passed by the firmware when no information other
-      than indices is available to associate an address with a device.
     - phy-connection-type : a string naming the controller/PHY interface type,
       i.e., "mii" (default), "rmii", "gmii", "rgmii", "rgmii-id", "sgmii",
       "tbi", or "rtbi".  This property is only really needed if the connection
@@ -1622,8 +1645,7 @@ platforms are moved over to use the flattened-device-tree model.
    - device_type : should be "network", "hldc", "uart", "transparent"
      "bisync", "atm", or "serial".
    - compatible : could be "ucc_geth" or "fsl_atm" and so on.
-   - model : should be "UCC".
-   - device-id : the ucc number(1-8), corresponding to UCCx in UM.
+   - cell-index : the ucc number(1-8), corresponding to UCCx in UM.
    - reg : Offset and length of the register set for the device
    - interrupts : <a b> where a is the interrupt number and b is a
      field that represents an encoding of the sense and level
@@ -1667,10 +1689,6 @@ platforms are moved over to use the flattened-device-tree model.
    - phy-handle : The phandle for the PHY connected to this controller.
 
    Recommended properties:
-   - linux,network-index : This is the intended "index" of this
-     network device.  This is used by the bootwrapper to interpret
-     MAC addresses passed by the firmware when no information other
-     than indices is available to associate an address with a device.
    - phy-connection-type : a string naming the controller/PHY interface type,
      i.e., "mii" (default), "rmii", "gmii", "rgmii", "rgmii-id" (Internal
      Delay), "rgmii-txid" (delay on TX only), "rgmii-rxid" (delay on RX only),
@@ -1680,8 +1698,7 @@ platforms are moved over to use the flattened-device-tree model.
 	ucc@2000 {
 		device_type = "network";
 		compatible = "ucc_geth";
-		model = "UCC";
-		device-id = <1>;
+		cell-index = <1>;
 		reg = <2000 200>;
 		interrupts = <a0 0>;
 		interrupt-parent = <700>;
@@ -1995,7 +2012,6 @@ platforms are moved over to use the flattened-device-tree model.
 		interrupts = <20 8>;
 		interrupt-parent = <&PIC>;
 		phy-handle = <&PHY0>;
-		linux,network-index = <0>;
 		fsl,cpm-command = <12000300>;
 	};
 
@@ -2217,12 +2233,6 @@ platforms are moved over to use the flattened-device-tree model.
 			  EMAC, that is the content of the current (bogus) "phy-port"
 			  property.
 
-    Recommended properties:
-    - linux,network-index : This is the intended "index" of this
-      network device.  This is used by the bootwrapper to interpret
-      MAC addresses passed by the firmware when no information other
-      than indices is available to associate an address with a device.
-
     Optional properties:
     - phy-address       : 1 cell, optional, MDIO address of the PHY. If absent,
 			  a search is performed.
@@ -2246,7 +2256,6 @@ platforms are moved over to use the flattened-device-tree model.
     Example:
 
 	EMAC0: ethernet@40000800 {
-		linux,network-index = <0>;
 		device_type = "network";
 		compatible = "ibm,emac-440gp", "ibm,emac";
 		interrupt-parent = <&UIC1>;
@@ -2817,9 +2826,528 @@ platforms are moved over to use the flattened-device-tree model.
 	   };
 
 
-   More devices will be defined as this spec matures.
+VII - Marvell Discovery mv64[345]6x System Controller chips
+===========================================================
+
+The Marvell mv64[345]60 series of system controller chips contain
+many of the peripherals needed to implement a complete computer
+system.  In this section, we define device tree nodes to describe
+the system controller chip itself and each of the peripherals
+which it contains.  Compatible string values for each node are
+prefixed with the string "marvell,", for Marvell Technology Group Ltd.
+
+1) The /system-controller node
+
+  This node is used to represent the system-controller and must be
+  present when the system uses a system contller chip. The top-level
+  system-controller node contains information that is global to all
+  devices within the system controller chip. The node name begins
+  with "system-controller" followed by the unit address, which is
+  the base address of the memory-mapped register set for the system
+  controller chip.
+
+  Required properties:
+
+    - ranges : Describes the translation of system controller addresses
+      for memory mapped registers.
+    - clock-frequency: Contains the main clock frequency for the system
+      controller chip.
+    - reg : This property defines the address and size of the
+      memory-mapped registers contained within the system controller
+      chip.  The address specified in the "reg" property should match
+      the unit address of the system-controller node.
+    - #address-cells : Address representation for system controller
+      devices.  This field represents the number of cells needed to
+      represent the address of the memory-mapped registers of devices
+      within the system controller chip.
+    - #size-cells : Size representation for for the memory-mapped
+      registers within the system controller chip.
+    - #interrupt-cells : Defines the width of cells used to represent
+      interrupts.
+
+  Optional properties:
+
+    - model : The specific model of the system controller chip.  Such
+      as, "mv64360", "mv64460", or "mv64560".
+    - compatible : A string identifying the compatibility identifiers
+      of the system controller chip.
+
+  The system-controller node contains child nodes for each system
+  controller device that the platform uses.  Nodes should not be created
+  for devices which exist on the system controller chip but are not used
+
+  Example Marvell Discovery mv64360 system-controller node:
+
+    system-controller@f1000000 { /* Marvell Discovery mv64360 */
+	    #address-cells = <1>;
+	    #size-cells = <1>;
+	    model = "mv64360";                      /* Default */
+	    compatible = "marvell,mv64360";
+	    clock-frequency = <133333333>;
+	    reg = <0xf1000000 0x10000>;
+	    virtual-reg = <0xf1000000>;
+	    ranges = <0x88000000 0x88000000 0x1000000 /* PCI 0 I/O Space */
+		    0x80000000 0x80000000 0x8000000 /* PCI 0 MEM Space */
+		    0xa0000000 0xa0000000 0x4000000 /* User FLASH */
+		    0x00000000 0xf1000000 0x0010000 /* Bridge's regs */
+		    0xf2000000 0xf2000000 0x0040000>;/* Integrated SRAM */
+
+	    [ child node definitions... ]
+    }
+
+2) Child nodes of /system-controller
+
+   a) Marvell Discovery MDIO bus
+
+   The MDIO is a bus to which the PHY devices are connected.  For each
+   device that exists on this bus, a child node should be created.  See
+   the definition of the PHY node below for an example of how to define
+   a PHY.
+
+   Required properties:
+     - #address-cells : Should be <1>
+     - #size-cells : Should be <0>
+     - device_type : Should be "mdio"
+     - compatible : Should be "marvell,mv64360-mdio"
+
+   Example:
+
+     mdio {
+	     #address-cells = <1>;
+	     #size-cells = <0>;
+	     device_type = "mdio";
+	     compatible = "marvell,mv64360-mdio";
+
+	     ethernet-phy@0 {
+		     ......
+	     };
+     };
+
+
+   b) Marvell Discovery ethernet controller
+
+   The Discover ethernet controller is described with two levels
+   of nodes.  The first level describes an ethernet silicon block
+   and the second level describes up to 3 ethernet nodes within
+   that block.  The reason for the multiple levels is that the
+   registers for the node are interleaved within a single set
+   of registers.  The "ethernet-block" level describes the
+   shared register set, and the "ethernet" nodes describe ethernet
+   port-specific properties.
+
+   Ethernet block node
+
+   Required properties:
+     - #address-cells : <1>
+     - #size-cells : <0>
+     - compatible : "marvell,mv64360-eth-block"
+     - reg : Offset and length of the register set for this block
+
+   Example Discovery Ethernet block node:
+     ethernet-block@2000 {
+	     #address-cells = <1>;
+	     #size-cells = <0>;
+	     compatible = "marvell,mv64360-eth-block";
+	     reg = <0x2000 0x2000>;
+	     ethernet@0 {
+		     .......
+	     };
+     };
+
+   Ethernet port node
+
+   Required properties:
+     - device_type : Should be "network".
+     - compatible : Should be "marvell,mv64360-eth".
+     - reg : Should be <0>, <1>, or <2>, according to which registers
+       within the silicon block the device uses.
+     - interrupts : <a> where a is the interrupt number for the port.
+     - interrupt-parent : the phandle for the interrupt controller
+       that services interrupts for this device.
+     - phy : the phandle for the PHY connected to this ethernet
+       controller.
+     - local-mac-address : 6 bytes, MAC address
+
+   Example Discovery Ethernet port node:
+     ethernet@0 {
+	     device_type = "network";
+	     compatible = "marvell,mv64360-eth";
+	     reg = <0>;
+	     interrupts = <32>;
+	     interrupt-parent = <&PIC>;
+	     phy = <&PHY0>;
+	     local-mac-address = [ 00 00 00 00 00 00 ];
+     };
+
+
+
+   c) Marvell Discovery PHY nodes
+
+   Required properties:
+     - device_type : Should be "ethernet-phy"
+     - interrupts : <a> where a is the interrupt number for this phy.
+     - interrupt-parent : the phandle for the interrupt controller that
+       services interrupts for this device.
+     - reg : The ID number for the phy, usually a small integer
+
+   Example Discovery PHY node:
+     ethernet-phy@1 {
+	     device_type = "ethernet-phy";
+	     compatible = "broadcom,bcm5421";
+	     interrupts = <76>;      /* GPP 12 */
+	     interrupt-parent = <&PIC>;
+	     reg = <1>;
+     };
+
+
+   d) Marvell Discovery SDMA nodes
+
+   Represent DMA hardware associated with the MPSC (multiprotocol
+   serial controllers).
+
+   Required properties:
+     - compatible : "marvell,mv64360-sdma"
+     - reg : Offset and length of the register set for this device
+     - interrupts : <a> where a is the interrupt number for the DMA
+       device.
+     - interrupt-parent : the phandle for the interrupt controller
+       that services interrupts for this device.
+
+   Example Discovery SDMA node:
+     sdma@4000 {
+	     compatible = "marvell,mv64360-sdma";
+	     reg = <0x4000 0xc18>;
+	     virtual-reg = <0xf1004000>;
+	     interrupts = <36>;
+	     interrupt-parent = <&PIC>;
+     };
+
+
+   e) Marvell Discovery BRG nodes
+
+   Represent baud rate generator hardware associated with the MPSC
+   (multiprotocol serial controllers).
+
+   Required properties:
+     - compatible : "marvell,mv64360-brg"
+     - reg : Offset and length of the register set for this device
+     - clock-src : A value from 0 to 15 which selects the clock
+       source for the baud rate generator.  This value corresponds
+       to the CLKS value in the BRGx configuration register.  See
+       the mv64x60 User's Manual.
+     - clock-frequence : The frequency (in Hz) of the baud rate
+       generator's input clock.
+     - current-speed : The current speed setting (presumably by
+       firmware) of the baud rate generator.
+
+   Example Discovery BRG node:
+     brg@b200 {
+	     compatible = "marvell,mv64360-brg";
+	     reg = <0xb200 0x8>;
+	     clock-src = <8>;
+	     clock-frequency = <133333333>;
+	     current-speed = <9600>;
+     };
+
+
+   f) Marvell Discovery CUNIT nodes
+
+   Represent the Serial Communications Unit device hardware.
+
+   Required properties:
+     - reg : Offset and length of the register set for this device
+
+   Example Discovery CUNIT node:
+     cunit@f200 {
+	     reg = <0xf200 0x200>;
+     };
+
+
+   g) Marvell Discovery MPSCROUTING nodes
+
+   Represent the Discovery's MPSC routing hardware
+
+   Required properties:
+     - reg : Offset and length of the register set for this device
+
+   Example Discovery CUNIT node:
+     mpscrouting@b500 {
+	     reg = <0xb400 0xc>;
+     };
+
+
+   h) Marvell Discovery MPSCINTR nodes
+
+   Represent the Discovery's MPSC DMA interrupt hardware registers
+   (SDMA cause and mask registers).
+
+   Required properties:
+     - reg : Offset and length of the register set for this device
 
-VII - Specifying interrupt information for devices
+   Example Discovery MPSCINTR node:
+     mpsintr@b800 {
+	     reg = <0xb800 0x100>;
+     };
+
+
+   i) Marvell Discovery MPSC nodes
+
+   Represent the Discovery's MPSC (Multiprotocol Serial Controller)
+   serial port.
+
+   Required properties:
+     - device_type : "serial"
+     - compatible : "marvell,mv64360-mpsc"
+     - reg : Offset and length of the register set for this device
+     - sdma : the phandle for the SDMA node used by this port
+     - brg : the phandle for the BRG node used by this port
+     - cunit : the phandle for the CUNIT node used by this port
+     - mpscrouting : the phandle for the MPSCROUTING node used by this port
+     - mpscintr : the phandle for the MPSCINTR node used by this port
+     - cell-index : the hardware index of this cell in the MPSC core
+     - max_idle : value needed for MPSC CHR3 (Maximum Frame Length)
+       register
+     - interrupts : <a> where a is the interrupt number for the MPSC.
+     - interrupt-parent : the phandle for the interrupt controller
+       that services interrupts for this device.
+
+   Example Discovery MPSCINTR node:
+     mpsc@8000 {
+	     device_type = "serial";
+	     compatible = "marvell,mv64360-mpsc";
+	     reg = <0x8000 0x38>;
+	     virtual-reg = <0xf1008000>;
+	     sdma = <&SDMA0>;
+	     brg = <&BRG0>;
+	     cunit = <&CUNIT>;
+	     mpscrouting = <&MPSCROUTING>;
+	     mpscintr = <&MPSCINTR>;
+	     cell-index = <0>;
+	     max_idle = <40>;
+	     interrupts = <40>;
+	     interrupt-parent = <&PIC>;
+     };
+
+
+   j) Marvell Discovery Watch Dog Timer nodes
+
+   Represent the Discovery's watchdog timer hardware
+
+   Required properties:
+     - compatible : "marvell,mv64360-wdt"
+     - reg : Offset and length of the register set for this device
+
+   Example Discovery Watch Dog Timer node:
+     wdt@b410 {
+	     compatible = "marvell,mv64360-wdt";
+	     reg = <0xb410 0x8>;
+     };
+
+
+   k) Marvell Discovery I2C nodes
+
+   Represent the Discovery's I2C hardware
+
+   Required properties:
+     - device_type : "i2c"
+     - compatible : "marvell,mv64360-i2c"
+     - reg : Offset and length of the register set for this device
+     - interrupts : <a> where a is the interrupt number for the I2C.
+     - interrupt-parent : the phandle for the interrupt controller
+       that services interrupts for this device.
+
+   Example Discovery I2C node:
+	     compatible = "marvell,mv64360-i2c";
+	     reg = <0xc000 0x20>;
+	     virtual-reg = <0xf100c000>;
+	     interrupts = <37>;
+	     interrupt-parent = <&PIC>;
+     };
+
+
+   l) Marvell Discovery PIC (Programmable Interrupt Controller) nodes
+
+   Represent the Discovery's PIC hardware
+
+   Required properties:
+     - #interrupt-cells : <1>
+     - #address-cells : <0>
+     - compatible : "marvell,mv64360-pic"
+     - reg : Offset and length of the register set for this device
+     - interrupt-controller
+
+   Example Discovery PIC node:
+     pic {
+	     #interrupt-cells = <1>;
+	     #address-cells = <0>;
+	     compatible = "marvell,mv64360-pic";
+	     reg = <0x0 0x88>;
+	     interrupt-controller;
+     };
+
+
+   m) Marvell Discovery MPP (Multipurpose Pins) multiplexing nodes
+
+   Represent the Discovery's MPP hardware
+
+   Required properties:
+     - compatible : "marvell,mv64360-mpp"
+     - reg : Offset and length of the register set for this device
+
+   Example Discovery MPP node:
+     mpp@f000 {
+	     compatible = "marvell,mv64360-mpp";
+	     reg = <0xf000 0x10>;
+     };
+
+
+   n) Marvell Discovery GPP (General Purpose Pins) nodes
+
+   Represent the Discovery's GPP hardware
+
+   Required properties:
+     - compatible : "marvell,mv64360-gpp"
+     - reg : Offset and length of the register set for this device
+
+   Example Discovery GPP node:
+     gpp@f000 {
+	     compatible = "marvell,mv64360-gpp";
+	     reg = <0xf100 0x20>;
+     };
+
+
+   o) Marvell Discovery PCI host bridge node
+
+   Represents the Discovery's PCI host bridge device.  The properties
+   for this node conform to Rev 2.1 of the PCI Bus Binding to IEEE
+   1275-1994.  A typical value for the compatible property is
+   "marvell,mv64360-pci".
+
+   Example Discovery PCI host bridge node
+     pci@80000000 {
+	     #address-cells = <3>;
+	     #size-cells = <2>;
+	     #interrupt-cells = <1>;
+	     device_type = "pci";
+	     compatible = "marvell,mv64360-pci";
+	     reg = <0xcf8 0x8>;
+	     ranges = <0x01000000 0x0        0x0
+			     0x88000000 0x0 0x01000000
+		       0x02000000 0x0 0x80000000
+			     0x80000000 0x0 0x08000000>;
+	     bus-range = <0 255>;
+	     clock-frequency = <66000000>;
+	     interrupt-parent = <&PIC>;
+	     interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+	     interrupt-map = <
+		     /* IDSEL 0x0a */
+		     0x5000 0 0 1 &PIC 80
+		     0x5000 0 0 2 &PIC 81
+		     0x5000 0 0 3 &PIC 91
+		     0x5000 0 0 4 &PIC 93
+
+		     /* IDSEL 0x0b */
+		     0x5800 0 0 1 &PIC 91
+		     0x5800 0 0 2 &PIC 93
+		     0x5800 0 0 3 &PIC 80
+		     0x5800 0 0 4 &PIC 81
+
+		     /* IDSEL 0x0c */
+		     0x6000 0 0 1 &PIC 91
+		     0x6000 0 0 2 &PIC 93
+		     0x6000 0 0 3 &PIC 80
+		     0x6000 0 0 4 &PIC 81
+
+		     /* IDSEL 0x0d */
+		     0x6800 0 0 1 &PIC 93
+		     0x6800 0 0 2 &PIC 80
+		     0x6800 0 0 3 &PIC 81
+		     0x6800 0 0 4 &PIC 91
+	     >;
+     };
+
+
+   p) Marvell Discovery CPU Error nodes
+
+   Represent the Discovery's CPU error handler device.
+
+   Required properties:
+     - compatible : "marvell,mv64360-cpu-error"
+     - reg : Offset and length of the register set for this device
+     - interrupts : the interrupt number for this device
+     - interrupt-parent : the phandle for the interrupt controller
+       that services interrupts for this device.
+
+   Example Discovery CPU Error node:
+     cpu-error@0070 {
+	     compatible = "marvell,mv64360-cpu-error";
+	     reg = <0x70 0x10 0x128 0x28>;
+	     interrupts = <3>;
+	     interrupt-parent = <&PIC>;
+     };
+
+
+   q) Marvell Discovery SRAM Controller nodes
+
+   Represent the Discovery's SRAM controller device.
+
+   Required properties:
+     - compatible : "marvell,mv64360-sram-ctrl"
+     - reg : Offset and length of the register set for this device
+     - interrupts : the interrupt number for this device
+     - interrupt-parent : the phandle for the interrupt controller
+       that services interrupts for this device.
+
+   Example Discovery SRAM Controller node:
+     sram-ctrl@0380 {
+	     compatible = "marvell,mv64360-sram-ctrl";
+	     reg = <0x380 0x80>;
+	     interrupts = <13>;
+	     interrupt-parent = <&PIC>;
+     };
+
+
+   r) Marvell Discovery PCI Error Handler nodes
+
+   Represent the Discovery's PCI error handler device.
+
+   Required properties:
+     - compatible : "marvell,mv64360-pci-error"
+     - reg : Offset and length of the register set for this device
+     - interrupts : the interrupt number for this device
+     - interrupt-parent : the phandle for the interrupt controller
+       that services interrupts for this device.
+
+   Example Discovery PCI Error Handler node:
+     pci-error@1d40 {
+	     compatible = "marvell,mv64360-pci-error";
+	     reg = <0x1d40 0x40 0xc28 0x4>;
+	     interrupts = <12>;
+	     interrupt-parent = <&PIC>;
+     };
+
+
+   s) Marvell Discovery Memory Controller nodes
+
+   Represent the Discovery's memory controller device.
+
+   Required properties:
+     - compatible : "marvell,mv64360-mem-ctrl"
+     - reg : Offset and length of the register set for this device
+     - interrupts : the interrupt number for this device
+     - interrupt-parent : the phandle for the interrupt controller
+       that services interrupts for this device.
+
+   Example Discovery Memory Controller node:
+     mem-ctrl@1400 {
+	     compatible = "marvell,mv64360-mem-ctrl";
+	     reg = <0x1400 0x60>;
+	     interrupts = <17>;
+	     interrupt-parent = <&PIC>;
+     };
+
+
+VIII - Specifying interrupt information for devices
 ===================================================
 
 The device tree represents the busses and devices of a hardware
@@ -2905,6 +3433,54 @@ encodings listed below:
 	2 =  high to low edge sensitive type enabled
 	3 =  low to high edge sensitive type enabled
 
+VIII - Specifying GPIO information for devices
+==============================================
+
+1) gpios property
+-----------------
+
+Nodes that makes use of GPIOs should define them using `gpios' property,
+format of which is: <&gpio-controller1-phandle gpio1-specifier
+		     &gpio-controller2-phandle gpio2-specifier
+		     0 /* holes are permitted, means no GPIO 3 */
+		     &gpio-controller4-phandle gpio4-specifier
+		     ...>;
+
+Note that gpio-specifier length is controller dependent.
+
+gpio-specifier may encode: bank, pin position inside the bank,
+whether pin is open-drain and whether pin is logically inverted.
+
+Example of the node using GPIOs:
+
+	node {
+		gpios = <&qe_pio_e 18 0>;
+	};
+
+In this example gpio-specifier is "18 0" and encodes GPIO pin number,
+and empty GPIO flags as accepted by the "qe_pio_e" gpio-controller.
+
+2) gpio-controller nodes
+------------------------
+
+Every GPIO controller node must have #gpio-cells property defined,
+this information will be used to translate gpio-specifiers.
+
+Example of two SOC GPIO banks defined as gpio-controller nodes:
+
+	qe_pio_a: gpio-controller@1400 {
+		#gpio-cells = <2>;
+		compatible = "fsl,qe-pario-bank-a", "fsl,qe-pario-bank";
+		reg = <0x1400 0x18>;
+		gpio-controller;
+	};
+
+	qe_pio_e: gpio-controller@1460 {
+		#gpio-cells = <2>;
+		compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
+		reg = <0x1460 0x18>;
+		gpio-controller;
+	};
 
 Appendix A - Sample SOC node for MPC8540
 ========================================

Documentation/powerpc/phyp-assisted-dump.txt

@@ -0,0 +1,127 @@
+
+                   Hypervisor-Assisted Dump
+                   ------------------------
+                       November 2007
+
+The goal of hypervisor-assisted dump is to enable the dump of
+a crashed system, and to do so from a fully-reset system, and
+to minimize the total elapsed time until the system is back
+in production use.
+
+As compared to kdump or other strategies, hypervisor-assisted
+dump offers several strong, practical advantages:
+
+-- Unlike kdump, the system has been reset, and loaded
+   with a fresh copy of the kernel.  In particular,
+   PCI and I/O devices have been reinitialized and are
+   in a clean, consistent state.
+-- As the dump is performed, the dumped memory becomes
+   immediately available to the system for normal use.
+-- After the dump is completed, no further reboots are
+   required; the system will be fully usable, and running
+   in it's normal, production mode on it normal kernel.
+
+The above can only be accomplished by coordination with,
+and assistance from the hypervisor. The procedure is
+as follows:
+
+-- When a system crashes, the hypervisor will save
+   the low 256MB of RAM to a previously registered
+   save region. It will also save system state, system
+   registers, and hardware PTE's.
+
+-- After the low 256MB area has been saved, the
+   hypervisor will reset PCI and other hardware state.
+   It will *not* clear RAM. It will then launch the
+   bootloader, as normal.
+
+-- The freshly booted kernel will notice that there
+   is a new node (ibm,dump-kernel) in the device tree,
+   indicating that there is crash data available from
+   a previous boot. It will boot into only 256MB of RAM,
+   reserving the rest of system memory.
+
+-- Userspace tools will parse /sys/kernel/release_region
+   and read /proc/vmcore to obtain the contents of memory,
+   which holds the previous crashed kernel. The userspace
+   tools may copy this info to disk, or network, nas, san,
+   iscsi, etc. as desired.
+
+   For Example: the values in /sys/kernel/release-region
+   would look something like this (address-range pairs).
+   CPU:0x177fee000-0x10000: HPTE:0x177ffe020-0x1000: /
+   DUMP:0x177fff020-0x10000000, 0x10000000-0x16F1D370A
+
+-- As the userspace tools complete saving a portion of
+   dump, they echo an offset and size to
+   /sys/kernel/release_region to release the reserved
+   memory back to general use.
+
+   An example of this is:
+     "echo 0x40000000 0x10000000 > /sys/kernel/release_region"
+   which will release 256MB at the 1GB boundary.
+
+Please note that the hypervisor-assisted dump feature
+is only available on Power6-based systems with recent
+firmware versions.
+
+Implementation details:
+----------------------
+
+During boot, a check is made to see if firmware supports
+this feature on this particular machine. If it does, then
+we check to see if a active dump is waiting for us. If yes
+then everything but 256 MB of RAM is reserved during early
+boot. This area is released once we collect a dump from user
+land scripts that are run. If there is dump data, then
+the /sys/kernel/release_region file is created, and
+the reserved memory is held.
+
+If there is no waiting dump data, then only the highest
+256MB of the ram is reserved as a scratch area. This area
+is *not* released: this region will be kept permanently
+reserved, so that it can act as a receptacle for a copy
+of the low 256MB in the case a crash does occur. See,
+however, "open issues" below, as to whether
+such a reserved region is really needed.
+
+Currently the dump will be copied from /proc/vmcore to a
+a new file upon user intervention. The starting address
+to be read and the range for each data point in provided
+in /sys/kernel/release_region.
+
+The tools to examine the dump will be same as the ones
+used for kdump.
+
+General notes:
+--------------
+Security: please note that there are potential security issues
+with any sort of dump mechanism. In particular, plaintext
+(unencrypted) data, and possibly passwords, may be present in
+the dump data. Userspace tools must take adequate precautions to
+preserve security.
+
+Open issues/ToDo:
+------------
+ o The various code paths that tell the hypervisor that a crash
+   occurred, vs. it simply being a normal reboot, should be
+   reviewed, and possibly clarified/fixed.
+
+ o Instead of using /sys/kernel, should there be a /sys/dump
+   instead? There is a dump_subsys being created by the s390 code,
+   perhaps the pseries code should use a similar layout as well.
+
+ o Is reserving a 256MB region really required? The goal of
+   reserving a 256MB scratch area is to make sure that no
+   important crash data is clobbered when the hypervisor
+   save low mem to the scratch area. But, if one could assure
+   that nothing important is located in some 256MB area, then
+   it would not need to be reserved. Something that can be
+   improved in subsequent versions.
+
+ o Still working the kdump team to integrate this with kdump,
+   some work remains but this would not affect the current
+   patches.
+
+ o Still need to write a shell script, to copy the dump away.
+   Currently I am parsing it manually.

arch/powerpc/Kconfig

@@ -49,6 +49,19 @@ config IRQ_PER_CPU
 	bool
 	default y
 
+config STACKTRACE_SUPPORT
+	bool
+	default y
+
+config TRACE_IRQFLAGS_SUPPORT
+	bool
+	depends on PPC64
+	default y
+
+config LOCKDEP_SUPPORT
+	bool
+	default y
+
 config RWSEM_GENERIC_SPINLOCK
 	bool
 
@@ -81,6 +94,11 @@ config GENERIC_FIND_NEXT_BIT
 	bool
 	default y
 
+config GENERIC_GPIO
+	bool
+	help
+	  Generic GPIO API support
+
 config ARCH_NO_VIRT_TO_BUS
 	def_bool PPC64
 
@@ -91,6 +109,7 @@ config PPC
 	select HAVE_OPROFILE
 	select HAVE_KPROBES
 	select HAVE_KRETPROBES
+	select HAVE_LMB
 
 config EARLY_PRINTK
 	bool
@@ -210,15 +229,6 @@ source kernel/Kconfig.hz
 source kernel/Kconfig.preempt
 source "fs/Kconfig.binfmt"
 
-# We optimistically allocate largepages from the VM, so make the limit
-# large enough (16MB). This badly named config option is actually
-# max order + 1
-config FORCE_MAX_ZONEORDER
-	int
-	depends on PPC64
-	default "9" if PPC_64K_PAGES
-	default "13"
-
 config HUGETLB_PAGE_SIZE_VARIABLE
 	bool
 	depends on HUGETLB_PAGE
@@ -307,6 +317,16 @@ config CRASH_DUMP
 
 	  Don't change this unless you know what you are doing.
 
+config PHYP_DUMP
+	bool "Hypervisor-assisted dump (EXPERIMENTAL)"
+	depends on PPC_PSERIES && EXPERIMENTAL
+	help
+	  Hypervisor-assisted dump is meant to be a kdump replacement
+	  offering robustness and speed not possible without system
+	  hypervisor assistence.
+
+	  If unsure, say "N"
+
 config PPCBUG_NVRAM
 	bool "Enable reading PPCBUG NVRAM during boot" if PPLUS || LOPEC
 	default y if PPC_PREP
@@ -381,6 +401,26 @@ config PPC_64K_PAGES
 	  while on hardware with such support, it will be used to map
 	  normal application pages.
 
+config FORCE_MAX_ZONEORDER
+	int "Maximum zone order"
+	default "9" if PPC_64K_PAGES
+	default "13" if PPC64 && !PPC_64K_PAGES
+	default "11"
+	help
+	  The kernel memory allocator divides physically contiguous memory
+	  blocks into "zones", where each zone is a power of two number of
+	  pages.  This option selects the largest power of two that the kernel
+	  keeps in the memory allocator.  If you need to allocate very large
+	  blocks of physically contiguous memory, then you may need to
+	  increase this value.
+
+	  This config option is actually maximum order plus one. For example,
+	  a value of 11 means that the largest free memory block is 2^10 pages.
+
+	  The page size is not necessarily 4KB.  For example, on 64-bit
+	  systems, 64KB pages can be enabled via CONFIG_PPC_64K_PAGES.  Keep
+	  this in mind when choosing a value for this option.
+
 config PPC_SUBPAGE_PROT
 	bool "Support setting protections for 4k subpages"
 	depends on PPC_64K_PAGES
@@ -490,6 +530,14 @@ config FSL_PCI
  	bool
 	select PPC_INDIRECT_PCI
 
+config 4xx_SOC
+	bool
+
+config FSL_LBC
+	bool
+	help
+	  Freescale Localbus support
+
 # Yes MCA RS/6000s exist but Linux-PPC does not currently support any
 config MCA
 	bool
@@ -663,22 +711,6 @@ config CONSISTENT_SIZE
 	hex "Size of consistent memory pool" if CONSISTENT_SIZE_BOOL
 	default "0x00200000" if NOT_COHERENT_CACHE
 
-config BOOT_LOAD_BOOL
-	bool "Set the boot link/load address"
-	depends on ADVANCED_OPTIONS && !PPC_MULTIPLATFORM
-	help
-	  This option allows you to set the initial load address of the zImage
-	  or zImage.initrd file.  This can be useful if you are on a board
-	  which has a small amount of memory.
-
-	  Say N here unless you know what you are doing.
-
-config BOOT_LOAD
-	hex "Link/load address for booting" if BOOT_LOAD_BOOL
-	default "0x00400000" if 40x || 8xx || 8260
-	default "0x01000000" if 44x
-	default "0x00800000"
-
 config PIN_TLB
 	bool "Pinned Kernel TLBs (860 ONLY)"
 	depends on ADVANCED_OPTIONS && 8xx

arch/powerpc/Kconfig.debug

@@ -269,7 +269,7 @@ config PPC_EARLY_DEBUG_CPM_ADDR
 	hex "CPM UART early debug transmit descriptor address"
 	depends on PPC_EARLY_DEBUG_CPM
 	default "0xfa202008" if PPC_EP88XC
-	default "0xf0000008" if CPM2
+	default "0xf0001ff8" if CPM2
 	default "0xff002008" if CPM1
 	help
 	  This specifies the address of the transmit descriptor

arch/powerpc/Makefile

@@ -71,13 +71,11 @@ endif
 
 LDFLAGS_vmlinux	:= -Bstatic
 
-CPPFLAGS-$(CONFIG_PPC32) := -Iarch/$(ARCH)
-AFLAGS-$(CONFIG_PPC32)	:= -Iarch/$(ARCH)
 CFLAGS-$(CONFIG_PPC64)	:= -mminimal-toc -mtraceback=none  -mcall-aixdesc
-CFLAGS-$(CONFIG_PPC32)	:= -Iarch/$(ARCH) -ffixed-r2 -mmultiple
-KBUILD_CPPFLAGS	+= $(CPPFLAGS-y)
-KBUILD_AFLAGS	+= $(AFLAGS-y)
-KBUILD_CFLAGS	+= -msoft-float -pipe $(CFLAGS-y)
+CFLAGS-$(CONFIG_PPC32)	:= -ffixed-r2 -mmultiple
+KBUILD_CPPFLAGS	+= -Iarch/$(ARCH)
+KBUILD_AFLAGS	+= -Iarch/$(ARCH)
+KBUILD_CFLAGS	+= -msoft-float -pipe -Iarch/$(ARCH) $(CFLAGS-y)
 CPP		= $(CC) -E $(KBUILD_CFLAGS)
 
 CHECKFLAGS	+= -m$(CONFIG_WORD_SIZE) -D__powerpc__ -D__powerpc$(CONFIG_WORD_SIZE)__
@@ -164,7 +162,7 @@ boot := arch/$(ARCH)/boot
 $(BOOT_TARGETS): vmlinux
 	$(Q)$(MAKE) ARCH=ppc64 $(build)=$(boot) $(patsubst %,$(boot)/%,$@)
 
-bootwrapper_install:
+bootwrapper_install %.dtb:
 	$(Q)$(MAKE) ARCH=ppc64 $(build)=$(boot) $(patsubst %,$(boot)/%,$@)
 
 define archhelp

arch/powerpc/boot/Makefile

@@ -40,6 +40,7 @@ $(obj)/ebony.o: BOOTCFLAGS += -mcpu=405
 $(obj)/cuboot-taishan.o: BOOTCFLAGS += -mcpu=405
 $(obj)/cuboot-katmai.o: BOOTCFLAGS += -mcpu=405
 $(obj)/treeboot-walnut.o: BOOTCFLAGS += -mcpu=405
+$(obj)/virtex405-head.o: BOOTCFLAGS += -mcpu=405
 
 
 zlib       := inffast.c inflate.c inftrees.c
@@ -64,7 +65,8 @@ src-plat := of.c cuboot-52xx.c cuboot-824x.c cuboot-83xx.c cuboot-85xx.c holly.c
 		cuboot-bamboo.c cuboot-mpc7448hpc2.c cuboot-taishan.c \
 		fixed-head.S ep88xc.c ep405.c \
 		cuboot-katmai.c cuboot-rainier.c redboot-8xx.c ep8248e.c \
-		cuboot-warp.c cuboot-85xx-cpm2.c
+		cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \
+		virtex405-head.S
 src-boot := $(src-wlib) $(src-plat) empty.c
 
 src-boot := $(addprefix $(obj)/, $(src-boot))
@@ -192,7 +194,7 @@ image-$(CONFIG_PPC_CHRP)		+= zImage.chrp
 image-$(CONFIG_PPC_EFIKA)		+= zImage.chrp
 image-$(CONFIG_PPC_PMAC)		+= zImage.pmac
 image-$(CONFIG_PPC_HOLLY)		+= zImage.holly
-image-$(CONFIG_PPC_PRPMC2800)		+= zImage.prpmc2800
+image-$(CONFIG_PPC_PRPMC2800)		+= dtbImage.prpmc2800
 image-$(CONFIG_PPC_ISERIES)		+= zImage.iseries
 image-$(CONFIG_DEFAULT_UIMAGE)		+= uImage
 
@@ -216,6 +218,7 @@ image-$(CONFIG_RAINIER)			+= cuImage.rainier
 image-$(CONFIG_TAISHAN)			+= cuImage.taishan
 image-$(CONFIG_KATMAI)			+= cuImage.katmai
 image-$(CONFIG_WARP)			+= cuImage.warp
+image-$(CONFIG_YOSEMITE)		+= cuImage.yosemite
 
 # Board ports in arch/powerpc/platform/8xx/Kconfig
 image-$(CONFIG_PPC_MPC86XADS)		+= cuImage.mpc866ads
@@ -255,6 +258,7 @@ image-$(CONFIG_TQM8555)			+= cuImage.tqm8555
 image-$(CONFIG_TQM8560)			+= cuImage.tqm8560
 image-$(CONFIG_SBC8548)			+= cuImage.sbc8548
 image-$(CONFIG_SBC8560)			+= cuImage.sbc8560
+image-$(CONFIG_KSI8560)			+= cuImage.ksi8560
 
 # Board ports in arch/powerpc/platform/embedded6xx/Kconfig
 image-$(CONFIG_STORCENTER)		+= cuImage.storcenter
@@ -285,11 +289,11 @@ $(obj)/zImage.%: vmlinux $(wrapperbits)
 	$(call if_changed,wrap,$*)
 
 # dtbImage% - a dtbImage is a zImage with an embedded device tree blob
-$(obj)/dtbImage.initrd.%: vmlinux $(wrapperbits) $(dtstree)/%.dts
-	$(call if_changed,wrap,$*,$(dtstree)/$*.dts,,$(obj)/ramdisk.image.gz)
+$(obj)/dtbImage.initrd.%: vmlinux $(wrapperbits) $(obj)/%.dtb
+	$(call if_changed,wrap,$*,,$(obj)/$*.dtb,$(obj)/ramdisk.image.gz)
 
-$(obj)/dtbImage.%: vmlinux $(wrapperbits) $(dtstree)/%.dts
-	$(call if_changed,wrap,$*,$(dtstree)/$*.dts)
+$(obj)/dtbImage.%: vmlinux $(wrapperbits) $(obj)/%.dtb
+	$(call if_changed,wrap,$*,,$(obj)/$*.dtb)
 
 # This cannot be in the root of $(src) as the zImage rule always adds a $(obj)
 # prefix
@@ -302,14 +306,24 @@ $(obj)/zImage.iseries: vmlinux
 $(obj)/uImage: vmlinux $(wrapperbits)
 	$(call if_changed,wrap,uboot)
 
-$(obj)/cuImage.%: vmlinux $(dtstree)/%.dts $(wrapperbits)
-	$(call if_changed,wrap,cuboot-$*,$(dtstree)/$*.dts)
+$(obj)/cuImage.%: vmlinux $(obj)/%.dtb $(wrapperbits)
+	$(call if_changed,wrap,cuboot-$*,,$(obj)/$*.dtb)
 
-$(obj)/treeImage.initrd.%: vmlinux $(dtstree)/%.dts $(wrapperbits)
-	$(call if_changed,wrap,treeboot-$*,$(dtstree)/$*.dts,,$(obj)/ramdisk.image.gz)
+$(obj)/simpleImage.initrd.%: vmlinux $(obj)/%.dtb $(wrapperbits)
+	$(call if_changed,wrap,simpleboot-$*,,$(obj)/$*.dtb,$(obj)/ramdisk.image.gz)
 
-$(obj)/treeImage.%: vmlinux $(dtstree)/%.dts $(wrapperbits)
-	$(call if_changed,wrap,treeboot-$*,$(dtstree)/$*.dts)
+$(obj)/simpleImage.%: vmlinux $(obj)/%.dtb $(wrapperbits)
+	$(call if_changed,wrap,simpleboot-$*,,$(obj)/$*.dtb)
+
+$(obj)/treeImage.initrd.%: vmlinux $(obj)/%.dtb $(wrapperbits)
+	$(call if_changed,wrap,treeboot-$*,,$(obj)/$*.dtb,$(obj)/ramdisk.image.gz)
+
+$(obj)/treeImage.%: vmlinux $(obj)/%.dtb $(wrapperbits)
+	$(call if_changed,wrap,treeboot-$*,,$(obj)/$*.dtb)
+
+# Rule to build device tree blobs
+$(obj)/%.dtb: $(dtstree)/%.dts $(obj)/dtc
+	$(obj)/dtc -O dtb -o $(obj)/$*.dtb -b 0 $(DTS_FLAGS) $(dtstree)/$*.dts
 
 # If there isn't a platform selected then just strip the vmlinux.
 ifeq (,$(image-y))
@@ -326,7 +340,7 @@ install: $(CONFIGURE) $(addprefix $(obj)/, $(image-y))
 
 # anything not in $(targets)
 clean-files += $(image-) $(initrd-) zImage zImage.initrd cuImage.* treeImage.* \
-	otheros.bld
+	otheros.bld *.dtb
 
 # clean up files cached by wrapper
 clean-kernel := vmlinux.strip vmlinux.bin

arch/powerpc/boot/bamboo.c

@@ -33,7 +33,8 @@ static void bamboo_fixups(void)
 	ibm440ep_fixup_clocks(sysclk, 11059200, 25000000);
 	ibm4xx_sdram_fixup_memsize();
 	ibm4xx_quiesce_eth((u32 *)0xef600e00, (u32 *)0xef600f00);
-	dt_fixup_mac_addresses(bamboo_mac0, bamboo_mac1);
+	dt_fixup_mac_address_by_alias("ethernet0", bamboo_mac0);
+	dt_fixup_mac_address_by_alias("ethernet1", bamboo_mac1);
 }
 
 void bamboo_init(void *mac0, void *mac1)

arch/powerpc/boot/cpm-serial.c

@@ -11,6 +11,7 @@
 #include "types.h"
 #include "io.h"
 #include "ops.h"
+#include "page.h"
 
 struct cpm_scc {
 	u32 gsmrl;
@@ -42,6 +43,22 @@ struct cpm_param {
 	u16 tbase;
 	u8 rfcr;
 	u8 tfcr;
+	u16 mrblr;
+	u32 rstate;
+	u8 res1[4];
+	u16 rbptr;
+	u8 res2[6];
+	u32 tstate;
+	u8 res3[4];
+	u16 tbptr;
+	u8 res4[6];
+	u16 maxidl;
+	u16 idlc;
+	u16 brkln;
+	u16 brkec;
+	u16 brkcr;
+	u16 rmask;
+	u8 res5[4];
 };
 
 struct cpm_bd {
@@ -54,10 +71,10 @@ static void *cpcr;
 static struct cpm_param *param;
 static struct cpm_smc *smc;
 static struct cpm_scc *scc;
-struct cpm_bd *tbdf, *rbdf;
+static struct cpm_bd *tbdf, *rbdf;
 static u32 cpm_cmd;
-static u8 *muram_start;
-static u32 muram_offset;
+static void *cbd_addr;
+static u32 cbd_offset;
 
 static void (*do_cmd)(int op);
 static void (*enable_port)(void);
@@ -119,20 +136,25 @@ static int cpm_serial_open(void)
 
 	out_8(&param->rfcr, 0x10);
 	out_8(&param->tfcr, 0x10);
-
-	rbdf = (struct cpm_bd *)muram_start;
-	rbdf->addr = (u8 *)(rbdf + 2);
+	out_be16(&param->mrblr, 1);
+	out_be16(&param->maxidl, 0);
+	out_be16(&param->brkec, 0);
+	out_be16(&param->brkln, 0);
+	out_be16(&param->brkcr, 0);
+
+	rbdf = cbd_addr;
+	rbdf->addr = (u8 *)rbdf - 1;
 	rbdf->sc = 0xa000;
 	rbdf->len = 1;
 
 	tbdf = rbdf + 1;
-	tbdf->addr = (u8 *)(rbdf + 2) + 1;
+	tbdf->addr = (u8 *)rbdf - 2;
 	tbdf->sc = 0x2000;
 	tbdf->len = 1;
 
 	sync();
-	out_be16(&param->rbase, muram_offset);
-	out_be16(&param->tbase, muram_offset + sizeof(struct cpm_bd));
+	out_be16(&param->rbase, cbd_offset);
+	out_be16(&param->tbase, cbd_offset + sizeof(struct cpm_bd));
 
 	do_cmd(CPM_CMD_INIT_RX_TX);
 
@@ -175,10 +197,12 @@ static unsigned char cpm_serial_getc(void)
 
 int cpm_console_init(void *devp, struct serial_console_data *scdp)
 {
-	void *reg_virt[2];
-	int is_smc = 0, is_cpm2 = 0, n;
-	unsigned long reg_phys;
+	void *vreg[2];
+	u32 reg[2];
+	int is_smc = 0, is_cpm2 = 0;
 	void *parent, *muram;
+	void *muram_addr;
+	unsigned long muram_offset, muram_size;
 
 	if (dt_is_compatible(devp, "fsl,cpm1-smc-uart")) {
 		is_smc = 1;
@@ -202,63 +226,64 @@ int cpm_console_init(void *devp, struct serial_console_data *scdp)
 	else
 		do_cmd = cpm1_cmd;
 
-	n = getprop(devp, "fsl,cpm-command", &cpm_cmd, 4);
-	if (n < 4)
+	if (getprop(devp, "fsl,cpm-command", &cpm_cmd, 4) < 4)
 		return -1;
 
-	n = getprop(devp, "virtual-reg", reg_virt, sizeof(reg_virt));
-	if (n < (int)sizeof(reg_virt)) {
-		for (n = 0; n < 2; n++) {
-			if (!dt_xlate_reg(devp, n, &reg_phys, NULL))
-				return -1;
-
-			reg_virt[n] = (void *)reg_phys;
-		}
-	}
+	if (dt_get_virtual_reg(devp, vreg, 2) < 2)
+		return -1;
 
 	if (is_smc)
-		smc = reg_virt[0];
+		smc = vreg[0];
 	else
-		scc = reg_virt[0];
+		scc = vreg[0];
 
-	param = reg_virt[1];
+	param = vreg[1];
 
 	parent = get_parent(devp);
 	if (!parent)
 		return -1;
 
-	n = getprop(parent, "virtual-reg", reg_virt, sizeof(reg_virt));
-	if (n < (int)sizeof(reg_virt)) {
-		if (!dt_xlate_reg(parent, 0, &reg_phys, NULL))
-			return -1;
-
-		reg_virt[0] = (void *)reg_phys;
-	}
-
-	cpcr = reg_virt[0];
+	if (dt_get_virtual_reg(parent, &cpcr, 1) < 1)
+		return -1;
 
 	muram = finddevice("/soc/cpm/muram/data");
 	if (!muram)
 		return -1;
 
 	/* For bootwrapper-compatible device trees, we assume that the first
-	 * entry has at least 18 bytes, and that #address-cells/#data-cells
+	 * entry has at least 128 bytes, and that #address-cells/#data-cells
 	 * is one for both parent and child.
 	 */
 
-	n = getprop(muram, "virtual-reg", reg_virt, sizeof(reg_virt));
-	if (n < (int)sizeof(reg_virt)) {
-		if (!dt_xlate_reg(muram, 0, &reg_phys, NULL))
-			return -1;
+	if (dt_get_virtual_reg(muram, &muram_addr, 1) < 1)
+		return -1;
 
-		reg_virt[0] = (void *)reg_phys;
-	}
+	if (getprop(muram, "reg", reg, 8) < 8)
+		return -1;
 
-	muram_start = reg_virt[0];
+	muram_offset = reg[0];
+	muram_size = reg[1];
 
-	n = getprop(muram, "reg", &muram_offset, 4);
-	if (n < 4)
-		return -1;
+	/* Store the buffer descriptors at the end of the first muram chunk.
+	 * For SMC ports on CPM2-based platforms, relocate the parameter RAM
+	 * just before the buffer descriptors.
+	 */
+
+	cbd_offset = muram_offset + muram_size - 2 * sizeof(struct cpm_bd);
+
+	if (is_cpm2 && is_smc) {
+		u16 *smc_base = (u16 *)param;
+		u16 pram_offset;
+
+		pram_offset = cbd_offset - 64;
+		pram_offset = _ALIGN_DOWN(pram_offset, 64);
+
+		disable_port();
+		out_be16(smc_base, pram_offset);
+		param = muram_addr - muram_offset + pram_offset;
+	}
+
+	cbd_addr = muram_addr - muram_offset + cbd_offset;
 
 	scdp->open = cpm_serial_open;
 	scdp->putc = cpm_serial_putc;

arch/powerpc/boot/cuboot-pq2.c

@@ -128,7 +128,7 @@ static void fixup_pci(void)
 	u8 *soc_regs;
 	int i, len;
 	void *node, *parent_node;
-	u32 naddr, nsize, mem_log2;
+	u32 naddr, nsize, mem_pow2, mem_mask;
 
 	node = finddevice("/pci");
 	if (!node || !dt_is_compatible(node, "fsl,pq2-pci"))
@@ -141,7 +141,7 @@ static void fixup_pci(void)
 
 	soc_regs = (u8 *)fsl_get_immr();
 	if (!soc_regs)
-		goto err;
+		goto unhandled;
 
 	dt_get_reg_format(node, &naddr, &nsize);
 	if (naddr != 3 || nsize != 2)
@@ -153,7 +153,7 @@ static void fixup_pci(void)
 
 	dt_get_reg_format(parent_node, &naddr, &nsize);
 	if (naddr != 1 || nsize != 1)
-		goto err;
+		goto unhandled;
 
 	len = getprop(node, "ranges", pci_ranges_buf,
 	              sizeof(pci_ranges_buf));
@@ -170,14 +170,20 @@ static void fixup_pci(void)
 	}
 
 	if (!mem || !mmio || !io)
-		goto err;
+		goto unhandled;
+	if (mem->size[1] != mmio->size[1])
+		goto unhandled;
+	if (mem->size[1] & (mem->size[1] - 1))
+		goto unhandled;
+	if (io->size[1] & (io->size[1] - 1))
+		goto unhandled;
 
 	if (mem->phys_addr + mem->size[1] == mmio->phys_addr)
 		mem_base = mem;
 	else if (mmio->phys_addr + mmio->size[1] == mem->phys_addr)
 		mem_base = mmio;
 	else
-		goto err;
+		goto unhandled;
 
 	out_be32(&pci_regs[1][0], mem_base->phys_addr | 1);
 	out_be32(&pci_regs[2][0], ~(mem->size[1] + mmio->size[1] - 1));
@@ -201,8 +207,9 @@ static void fixup_pci(void)
 	out_le32(&pci_regs[0][58], 0);
 	out_le32(&pci_regs[0][60], 0);
 
-	mem_log2 = 1 << (__ilog2_u32(bd.bi_memsize - 1) + 1);
-	out_le32(&pci_regs[0][62], 0xa0000000 | ~((1 << (mem_log2 - 12)) - 1));
+	mem_pow2 = 1 << (__ilog2_u32(bd.bi_memsize - 1) + 1);
+	mem_mask = ~(mem_pow2 - 1) >> 12;
+	out_le32(&pci_regs[0][62], 0xa0000000 | mem_mask);
 
 	/* If PCI is disabled, drive RST high to enable. */
 	if (!(in_le32(&pci_regs[0][32]) & 1)) {
@@ -228,7 +235,11 @@ static void fixup_pci(void)
 	return;
 
 err:
-	printf("Bad PCI node\r\n");
+	printf("Bad PCI node -- using existing firmware setup.\r\n");
+	return;
+
+unhandled:
+	printf("Unsupported PCI node -- using existing firmware setup.\r\n");
 }
 
 static void pq2_platform_fixups(void)

arch/powerpc/boot/cuboot-rainier.c

@@ -42,7 +42,8 @@ static void rainier_fixups(void)
 	ibm440ep_fixup_clocks(sysclk, 11059200, 50000000);
 	ibm4xx_fixup_ebc_ranges("/plb/opb/ebc");
 	ibm4xx_denali_fixup_memsize();
-	dt_fixup_mac_addresses(&bd.bi_enetaddr, &bd.bi_enet1addr);
+	dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr);
+	dt_fixup_mac_address_by_alias("ethernet1", bd.bi_enet1addr);
 }
 
 void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,

arch/powerpc/boot/cuboot-sequoia.c

@@ -42,7 +42,8 @@ static void sequoia_fixups(void)
 	ibm440ep_fixup_clocks(sysclk, 11059200, 50000000);
 	ibm4xx_fixup_ebc_ranges("/plb/opb/ebc");
 	ibm4xx_denali_fixup_memsize();
-	dt_fixup_mac_addresses(&bd.bi_enetaddr, &bd.bi_enet1addr);
+	dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr);
+	dt_fixup_mac_address_by_alias("ethernet1", bd.bi_enet1addr);
 }
 
 void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,

arch/powerpc/boot/cuboot-taishan.c

@@ -40,7 +40,8 @@ static void taishan_fixups(void)
 
 	ibm4xx_sdram_fixup_memsize();
 
-	dt_fixup_mac_addresses(bd.bi_enetaddr, bd.bi_enet1addr);
+	dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr);
+	dt_fixup_mac_address_by_alias("ethernet1", bd.bi_enet1addr);
 
 	ibm4xx_fixup_ebc_ranges("/plb/opb/ebc");
 }

arch/powerpc/boot/cuboot-warp.c

@@ -24,7 +24,7 @@ static void warp_fixups(void)
 	ibm440ep_fixup_clocks(sysclk, 11059200, 50000000);
 	ibm4xx_sdram_fixup_memsize();
 	ibm4xx_fixup_ebc_ranges("/plb/opb/ebc");
-	dt_fixup_mac_addresses(&bd.bi_enetaddr);
+	dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr);
 }
 
 

arch/powerpc/boot/cuboot-yosemite.c

@@ -0,0 +1,44 @@
+/*
+ * Old U-boot compatibility for Yosemite
+ *
+ * Author: Josh Boyer <jwboyer@linux.vnet.ibm.com>
+ *
+ * Copyright 2008 IBM Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include "ops.h"
+#include "stdio.h"
+#include "4xx.h"
+#include "44x.h"
+#include "cuboot.h"
+
+#define TARGET_4xx
+#define TARGET_44x
+#include "ppcboot.h"
+
+static bd_t bd;
+
+static void yosemite_fixups(void)
+{
+	unsigned long sysclk = 66666666;
+
+	ibm440ep_fixup_clocks(sysclk, 11059200, 50000000);
+	ibm4xx_sdram_fixup_memsize();
+	ibm4xx_quiesce_eth((u32 *)0xef600e00, (u32 *)0xef600f00);
+	dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr);
+	dt_fixup_mac_address_by_alias("ethernet1", bd.bi_enet1addr);
+}
+
+void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
+		unsigned long r6, unsigned long r7)
+{
+	CUBOOT_INIT();
+	platform_ops.fixups = yosemite_fixups;
+	platform_ops.exit = ibm44x_dbcr_reset;
+	fdt_init(_dtb_start);
+	serial_console_init();
+}

arch/powerpc/boot/devtree.c

@@ -350,3 +350,23 @@ int dt_is_compatible(void *node, const char *compat)
 
 	return 0;
 }
+
+int dt_get_virtual_reg(void *node, void **addr, int nres)
+{
+	unsigned long xaddr;
+	int n;
+
+	n = getprop(node, "virtual-reg", addr, nres * 4);
+	if (n > 0)
+		return n / 4;
+
+	for (n = 0; n < nres; n++) {
+		if (!dt_xlate_reg(node, n, &xaddr, NULL))
+			break;
+
+		addr[n] = (void *)xaddr;
+	}
+
+	return n;
+}
+

arch/powerpc/boot/dts/bamboo.dts

@@ -204,7 +204,6 @@
 			};
 
 			EMAC0: ethernet@ef600e00 {
-				linux,network-index = <0>;
 				device_type = "network";
 				compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac";
 				interrupt-parent = <&UIC1>;
@@ -225,7 +224,6 @@
 			};
 
 			EMAC1: ethernet@ef600f00 {
-				linux,network-index = <1>;
 				device_type = "network";
 				compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac";
 				interrupt-parent = <&UIC1>;

arch/powerpc/boot/dts/canyonlands.dts

@@ -0,0 +1,402 @@
+/*
+ * Device Tree Source for AMCC Canyonlands (460EX)
+ *
+ * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without
+ * any warranty of any kind, whether express or implied.
+ */
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <1>;
+	model = "amcc,canyonlands";
+	compatible = "amcc,canyonlands";
+	dcr-parent = <&/cpus/cpu@0>;
+
+	aliases {
+		ethernet0 = &EMAC0;
+		ethernet1 = &EMAC1;
+		serial0 = &UART0;
+		serial1 = &UART1;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			model = "PowerPC,460EX";
+			reg = <0>;
+			clock-frequency = <0>; /* Filled in by U-Boot */
+			timebase-frequency = <0>; /* Filled in by U-Boot */
+			i-cache-line-size = <20>;
+			d-cache-line-size = <20>;
+			i-cache-size = <8000>;
+			d-cache-size = <8000>;
+			dcr-controller;
+			dcr-access-method = "native";
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0 0 0>; /* Filled in by U-Boot */
+	};
+
+	UIC0: interrupt-controller0 {
+		compatible = "ibm,uic-460ex","ibm,uic";
+		interrupt-controller;
+		cell-index = <0>;
+		dcr-reg = <0c0 009>;
+		#address-cells = <0>;
+		#size-cells = <0>;
+		#interrupt-cells = <2>;
+	};
+
+	UIC1: interrupt-controller1 {
+		compatible = "ibm,uic-460ex","ibm,uic";
+		interrupt-controller;
+		cell-index = <1>;
+		dcr-reg = <0d0 009>;
+		#address-cells = <0>;
+		#size-cells = <0>;
+		#interrupt-cells = <2>;
+		interrupts = <1e 4 1f 4>; /* cascade */
+		interrupt-parent = <&UIC0>;
+	};
+
+	UIC2: interrupt-controller2 {
+		compatible = "ibm,uic-460ex","ibm,uic";
+		interrupt-controller;
+		cell-index = <2>;
+		dcr-reg = <0e0 009>;
+		#address-cells = <0>;
+		#size-cells = <0>;
+		#interrupt-cells = <2>;
+		interrupts = <a 4 b 4>; /* cascade */
+		interrupt-parent = <&UIC0>;
+	};
+
+	UIC3: interrupt-controller3 {
+		compatible = "ibm,uic-460ex","ibm,uic";
+		interrupt-controller;
+		cell-index = <3>;
+		dcr-reg = <0f0 009>;
+		#address-cells = <0>;
+		#size-cells = <0>;
+		#interrupt-cells = <2>;
+		interrupts = <10 4 11 4>; /* cascade */
+		interrupt-parent = <&UIC0>;
+	};
+
+	SDR0: sdr {
+		compatible = "ibm,sdr-460ex";
+		dcr-reg = <00e 002>;
+	};
+
+	CPR0: cpr {
+		compatible = "ibm,cpr-460ex";
+		dcr-reg = <00c 002>;
+	};
+
+	plb {
+		compatible = "ibm,plb-460ex", "ibm,plb4";
+		#address-cells = <2>;
+		#size-cells = <1>;
+		ranges;
+		clock-frequency = <0>; /* Filled in by U-Boot */
+
+		SDRAM0: sdram {
+			compatible = "ibm,sdram-460ex", "ibm,sdram-405gp";
+			dcr-reg = <010 2>;
+		};
+
+		MAL0: mcmal {
+			compatible = "ibm,mcmal-460ex", "ibm,mcmal2";
+			dcr-reg = <180 62>;
+			num-tx-chans = <2>;
+			num-rx-chans = <10>;
+			#address-cells = <0>;
+			#size-cells = <0>;
+			interrupt-parent = <&UIC2>;
+			interrupts = <	/*TXEOB*/ 6 4
+					/*RXEOB*/ 7 4
+					/*SERR*/  3 4
+					/*TXDE*/  4 4
+					/*RXDE*/  5 4>;
+		};
+
+		POB0: opb {
+			compatible = "ibm,opb-460ex", "ibm,opb";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <b0000000 4 b0000000 50000000>;
+			clock-frequency = <0>; /* Filled in by U-Boot */
+
+			EBC0: ebc {
+				compatible = "ibm,ebc-460ex", "ibm,ebc";
+				dcr-reg = <012 2>;
+				#address-cells = <2>;
+				#size-cells = <1>;
+				clock-frequency = <0>; /* Filled in by U-Boot */
+				interrupts = <6 4>;
+				interrupt-parent = <&UIC1>;
+			};
+
+			UART0: serial@ef600300 {
+				device_type = "serial";
+				compatible = "ns16550";
+				reg = <ef600300 8>;
+				virtual-reg = <ef600300>;
+				clock-frequency = <0>; /* Filled in by U-Boot */
+				current-speed = <0>; /* Filled in by U-Boot */
+				interrupt-parent = <&UIC1>;
+				interrupts = <1 4>;
+			};
+
+			UART1: serial@ef600400 {
+				device_type = "serial";
+				compatible = "ns16550";
+				reg = <ef600400 8>;
+				virtual-reg = <ef600400>;
+				clock-frequency = <0>; /* Filled in by U-Boot */
+				current-speed = <0>; /* Filled in by U-Boot */
+				interrupt-parent = <&UIC0>;
+				interrupts = <1 4>;
+			};
+
+			UART2: serial@ef600500 {
+				device_type = "serial";
+				compatible = "ns16550";
+				reg = <ef600500 8>;
+				virtual-reg = <ef600500>;
+				clock-frequency = <0>; /* Filled in by U-Boot */
+				current-speed = <0>; /* Filled in by U-Boot */
+				interrupt-parent = <&UIC1>;
+				interrupts = <1d 4>;
+			};
+
+			UART3: serial@ef600600 {
+				device_type = "serial";
+				compatible = "ns16550";
+				reg = <ef600600 8>;
+				virtual-reg = <ef600600>;
+				clock-frequency = <0>; /* Filled in by U-Boot */
+				current-speed = <0>; /* Filled in by U-Boot */
+				interrupt-parent = <&UIC1>;
+				interrupts = <1e 4>;
+			};
+
+			IIC0: i2c@ef600700 {
+				compatible = "ibm,iic-460ex", "ibm,iic";
+				reg = <ef600700 14>;
+				interrupt-parent = <&UIC0>;
+				interrupts = <2 4>;
+			};
+
+			IIC1: i2c@ef600800 {
+				compatible = "ibm,iic-460ex", "ibm,iic";
+				reg = <ef600800 14>;
+				interrupt-parent = <&UIC0>;
+				interrupts = <3 4>;
+			};
+
+			ZMII0: emac-zmii@ef600d00 {
+				compatible = "ibm,zmii-460ex", "ibm,zmii";
+				reg = <ef600d00 c>;
+			};
+
+			RGMII0: emac-rgmii@ef601500 {
+				compatible = "ibm,rgmii-460ex", "ibm,rgmii";
+				reg = <ef601500 8>;
+				has-mdio;
+			};
+
+			TAH0: emac-tah@ef601350 {
+				compatible = "ibm,tah-460ex", "ibm,tah";
+				reg = <ef601350 30>;
+			};
+
+			TAH1: emac-tah@ef601450 {
+				compatible = "ibm,tah-460ex", "ibm,tah";
+				reg = <ef601450 30>;
+			};
+
+			EMAC0: ethernet@ef600e00 {
+				device_type = "network";
+				compatible = "ibm,emac-460ex", "ibm,emac4";
+				interrupt-parent = <&EMAC0>;
+				interrupts = <0 1>;
+				#interrupt-cells = <1>;
+				#address-cells = <0>;
+				#size-cells = <0>;
+				interrupt-map = </*Status*/ 0 &UIC2 10 4
+						 /*Wake*/   1 &UIC2 14 4>;
+				reg = <ef600e00 70>;
+				local-mac-address = [000000000000]; /* Filled in by U-Boot */
+				mal-device = <&MAL0>;
+				mal-tx-channel = <0>;
+				mal-rx-channel = <0>;
+				cell-index = <0>;
+				max-frame-size = <2328>;
+				rx-fifo-size = <1000>;
+				tx-fifo-size = <800>;
+				phy-mode = "rgmii";
+				phy-map = <00000000>;
+				rgmii-device = <&RGMII0>;
+				rgmii-channel = <0>;
+				tah-device = <&TAH0>;
+				tah-channel = <0>;
+				has-inverted-stacr-oc;
+				has-new-stacr-staopc;
+			};
+
+			EMAC1: ethernet@ef600f00 {
+				device_type = "network";
+				compatible = "ibm,emac-460ex", "ibm,emac4";
+				interrupt-parent = <&EMAC1>;
+				interrupts = <0 1>;
+				#interrupt-cells = <1>;
+				#address-cells = <0>;
+				#size-cells = <0>;
+				interrupt-map = </*Status*/ 0 &UIC2 11 4
+						 /*Wake*/   1 &UIC2 15 4>;
+				reg = <ef600f00 70>;
+				local-mac-address = [000000000000]; /* Filled in by U-Boot */
+				mal-device = <&MAL0>;
+				mal-tx-channel = <1>;
+				mal-rx-channel = <8>;
+				cell-index = <1>;
+				max-frame-size = <2328>;
+				rx-fifo-size = <1000>;
+				tx-fifo-size = <800>;
+				phy-mode = "rgmii";
+				phy-map = <00000000>;
+				rgmii-device = <&RGMII0>;
+				rgmii-channel = <1>;
+				tah-device = <&TAH1>;
+				tah-channel = <1>;
+				has-inverted-stacr-oc;
+				has-new-stacr-staopc;
+				mdio-device = <&EMAC0>;
+			};
+		};
+
+		PCIX0: pci@c0ec00000 {
+			device_type = "pci";
+			#interrupt-cells = <1>;
+			#size-cells = <2>;
+			#address-cells = <3>;
+			compatible = "ibm,plb-pcix-460ex", "ibm,plb-pcix";
+			primary;
+			large-inbound-windows;
+			enable-msi-hole;
+			reg = <c 0ec00000   8	/* Config space access */
+			       0 0 0		/* no IACK cycles */
+			       c 0ed00000   4   /* Special cycles */
+			       c 0ec80000 100	/* Internal registers */
+			       c 0ec80100  fc>;	/* Internal messaging registers */
+
+			/* Outbound ranges, one memory and one IO,
+			 * later cannot be changed
+			 */
+			ranges = <02000000 0 80000000 0000000d 80000000 0 80000000
+				  01000000 0 00000000 0000000c 08000000 0 00010000>;
+
+			/* Inbound 2GB range starting at 0 */
+			dma-ranges = <42000000 0 0 0 0 0 80000000>;
+
+			/* This drives busses 0 to 0x3f */
+			bus-range = <0 3f>;
+
+			/* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */
+			interrupt-map-mask = <0000 0 0 0>;
+			interrupt-map = < 0000 0 0 0 &UIC1 0 8 >;
+		};
+
+		PCIE0: pciex@d00000000 {
+			device_type = "pci";
+			#interrupt-cells = <1>;
+			#size-cells = <2>;
+			#address-cells = <3>;
+			compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
+			primary;
+			port = <0>; /* port number */
+			reg = <d 00000000 20000000	/* Config space access */
+			       c 08010000 00001000>;	/* Registers */
+			dcr-reg = <100 020>;
+			sdr-base = <300>;
+
+			/* Outbound ranges, one memory and one IO,
+			 * later cannot be changed
+			 */
+			ranges = <02000000 0 80000000 0000000e 00000000 0 80000000
+				  01000000 0 00000000 0000000f 80000000 0 00010000>;
+
+			/* Inbound 2GB range starting at 0 */
+			dma-ranges = <42000000 0 0 0 0 0 80000000>;
+
+			/* This drives busses 40 to 0x7f */
+			bus-range = <40 7f>;
+
+			/* Legacy interrupts (note the weird polarity, the bridge seems
+			 * to invert PCIe legacy interrupts).
+			 * We are de-swizzling here because the numbers are actually for
+			 * port of the root complex virtual P2P bridge. But I want
+			 * to avoid putting a node for it in the tree, so the numbers
+			 * below are basically de-swizzled numbers.
+			 * The real slot is on idsel 0, so the swizzling is 1:1
+			 */
+			interrupt-map-mask = <0000 0 0 7>;
+			interrupt-map = <
+				0000 0 0 1 &UIC3 c 4 /* swizzled int A */
+				0000 0 0 2 &UIC3 d 4 /* swizzled int B */
+				0000 0 0 3 &UIC3 e 4 /* swizzled int C */
+				0000 0 0 4 &UIC3 f 4 /* swizzled int D */>;
+		};
+
+		PCIE1: pciex@d20000000 {
+			device_type = "pci";
+			#interrupt-cells = <1>;
+			#size-cells = <2>;
+			#address-cells = <3>;
+			compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
+			primary;
+			port = <1>; /* port number */
+			reg = <d 20000000 20000000	/* Config space access */
+			       c 08011000 00001000>;	/* Registers */
+			dcr-reg = <120 020>;
+			sdr-base = <340>;
+
+			/* Outbound ranges, one memory and one IO,
+			 * later cannot be changed
+			 */
+			ranges = <02000000 0 80000000 0000000e 80000000 0 80000000
+				  01000000 0 00000000 0000000f 80010000 0 00010000>;
+
+			/* Inbound 2GB range starting at 0 */
+			dma-ranges = <42000000 0 0 0 0 0 80000000>;
+
+			/* This drives busses 80 to 0xbf */
+			bus-range = <80 bf>;
+
+			/* Legacy interrupts (note the weird polarity, the bridge seems
+			 * to invert PCIe legacy interrupts).
+			 * We are de-swizzling here because the numbers are actually for
+			 * port of the root complex virtual P2P bridge. But I want
+			 * to avoid putting a node for it in the tree, so the numbers
+			 * below are basically de-swizzled numbers.
+			 * The real slot is on idsel 0, so the swizzling is 1:1
+			 */
+			interrupt-map-mask = <0000 0 0 7>;
+			interrupt-map = <
+				0000 0 0 1 &UIC3 10 4 /* swizzled int A */
+				0000 0 0 2 &UIC3 11 4 /* swizzled int B */
+				0000 0 0 3 &UIC3 12 4 /* swizzled int C */
+				0000 0 0 4 &UIC3 13 4 /* swizzled int D */>;
+		};
+	};
+};

arch/powerpc/boot/dts/ebony.dts

@@ -241,7 +241,6 @@
 			};
 
 			EMAC0: ethernet@40000800 {
-				linux,network-index = <0>;
 				device_type = "network";
 				compatible = "ibm,emac-440gp", "ibm,emac";
 				interrupt-parent = <&UIC1>;
@@ -261,7 +260,6 @@
 				zmii-channel = <0>;
 			};
 			EMAC1: ethernet@40000900 {
-				linux,network-index = <1>;
 				device_type = "network";
 				compatible = "ibm,emac-440gp", "ibm,emac";
 				interrupt-parent = <&UIC1>;

arch/powerpc/boot/dts/ep8248e.dts

@@ -121,8 +121,7 @@
 
 				data@0 {
 					compatible = "fsl,cpm-muram-data";
-					reg = <0 0x1100 0x1140
-					       0xec0 0x9800 0x800>;
+					reg = <0 0x2000 0x9800 0x800>;
 				};
 			};
 
@@ -138,7 +137,7 @@
 				device_type = "serial";
 				compatible = "fsl,mpc8248-smc-uart",
 				             "fsl,cpm2-smc-uart";
-				reg = <0x11a80 0x20 0x1100 0x40>;
+				reg = <0x11a80 0x20 0x87fc 2>;
 				interrupts = <4 8>;
 				interrupt-parent = <&PIC>;
 				fsl,cpm-brg = <7>;

arch/powerpc/boot/dts/ep88xc.dts

@@ -2,7 +2,7 @@
  * EP88xC Device Tree Source
  *
  * Copyright 2006 MontaVista Software, Inc.
- * Copyright 2007 Freescale Semiconductor, Inc.
+ * Copyright 2007,2008 Freescale Semiconductor, Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -10,6 +10,7 @@
  * option) any later version.
  */
 
+/dts-v1/;
 
 / {
 	model = "EP88xC";
@@ -23,44 +24,44 @@
 
 		PowerPC,885@0 {
 			device_type = "cpu";
-			reg = <0>;
-			d-cache-line-size = <d#16>;
-			i-cache-line-size = <d#16>;
-			d-cache-size = <d#8192>;
-			i-cache-size = <d#8192>;
+			reg = <0x0>;
+			d-cache-line-size = <16>;
+			i-cache-line-size = <16>;
+			d-cache-size = <8192>;
+			i-cache-size = <8192>;
 			timebase-frequency = <0>;
 			bus-frequency = <0>;
 			clock-frequency = <0>;
-			interrupts = <f 2>;	// decrementer interrupt
+			interrupts = <15 2>;	// decrementer interrupt
 			interrupt-parent = <&PIC>;
 		};
 	};
 
 	memory {
 		device_type = "memory";
-		reg = <0 0>;
+		reg = <0x0 0x0>;
 	};
 
 	localbus@fa200100 {
 		compatible = "fsl,mpc885-localbus", "fsl,pq1-localbus";
 		#address-cells = <2>;
 		#size-cells = <1>;
-		reg = <fa200100 40>;
+		reg = <0xfa200100 0x40>;
 
 		ranges = <
-			0 0 fc000000 04000000
-			3 0 fa000000 01000000
+			0x0 0x0 0xfc000000 0x4000000
+			0x3 0x0 0xfa000000 0x1000000
 		>;
 
 		flash@0,2000000 {
 			compatible = "cfi-flash";
-			reg = <0 2000000 2000000>;
+			reg = <0x0 0x2000000 0x2000000>;
 			bank-width = <4>;
 			device-width = <2>;
 		};
 
 		board-control@3,400000 {
-			reg = <3 400000 10>;
+			reg = <0x3 0x400000 0x10>;
 			compatible = "fsl,ep88xc-bcsr";
 		};
 	};
@@ -70,25 +71,25 @@
 		#address-cells = <1>;
 		#size-cells = <1>;
 		device_type = "soc";
-		ranges = <0 fa200000 00004000>;
+		ranges = <0x0 0xfa200000 0x4000>;
 		bus-frequency = <0>;
 
 		// Temporary -- will go away once kernel uses ranges for get_immrbase().
-		reg = <fa200000 4000>;
+		reg = <0xfa200000 0x4000>;
 
 		mdio@e00 {
 			compatible = "fsl,mpc885-fec-mdio", "fsl,pq1-fec-mdio";
-			reg = <e00 188>;
+			reg = <0xe00 0x188>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 
 			PHY0: ethernet-phy@0 {
-				reg = <0>;
+				reg = <0x0>;
 				device_type = "ethernet-phy";
 			};
 
 			PHY1: ethernet-phy@1 {
-				reg = <1>;
+				reg = <0x1>;
 				device_type = "ethernet-phy";
 			};
 		};
@@ -97,7 +98,7 @@
 			device_type = "network";
 			compatible = "fsl,mpc885-fec-enet",
 			             "fsl,pq1-fec-enet";
-			reg = <e00 188>;
+			reg = <0xe00 0x188>;
 			local-mac-address = [ 00 00 00 00 00 00 ];
 			interrupts = <3 1>;
 			interrupt-parent = <&PIC>;
@@ -109,7 +110,7 @@
 			device_type = "network";
 			compatible = "fsl,mpc885-fec-enet",
 			             "fsl,pq1-fec-enet";
-			reg = <1e00 188>;
+			reg = <0x1e00 0x188>;
 			local-mac-address = [ 00 00 00 00 00 00 ];
 			interrupts = <7 1>;
 			interrupt-parent = <&PIC>;
@@ -120,7 +121,7 @@
 		PIC: interrupt-controller@0 {
 			interrupt-controller;
 			#interrupt-cells = <2>;
-			reg = <0 24>;
+			reg = <0x0 0x24>;
 			compatible = "fsl,mpc885-pic", "fsl,pq1-pic";
 		};
 
@@ -130,29 +131,29 @@
 			#size-cells = <2>;
 			compatible = "fsl,pq-pcmcia";
 			device_type = "pcmcia";
-			reg = <80 80>;
+			reg = <0x80 0x80>;
 			interrupt-parent = <&PIC>;
-			interrupts = <d 1>;
+			interrupts = <13 1>;
 		};
 
 		cpm@9c0 {
 			#address-cells = <1>;
 			#size-cells = <1>;
 			compatible = "fsl,mpc885-cpm", "fsl,cpm1";
-			command-proc = <9c0>;
+			command-proc = <0x9c0>;
 			interrupts = <0>;	// cpm error interrupt
 			interrupt-parent = <&CPM_PIC>;
-			reg = <9c0 40>;
+			reg = <0x9c0 0x40>;
 			ranges;
 
 			muram@2000 {
 				#address-cells = <1>;
 				#size-cells = <1>;
-				ranges = <0 2000 2000>;
+				ranges = <0x0 0x2000 0x2000>;
 
 				data@0 {
 					compatible = "fsl,cpm-muram-data";
-					reg = <0 1c00>;
+					reg = <0x0 0x1c00>;
 				};
 			};
 
@@ -160,7 +161,7 @@
 				compatible = "fsl,mpc885-brg",
 				             "fsl,cpm1-brg",
 				             "fsl,cpm-brg";
-				reg = <9f0 10>;
+				reg = <0x9f0 0x10>;
 			};
 
 			CPM_PIC: interrupt-controller@930 {
@@ -168,7 +169,7 @@
 				#interrupt-cells = <1>;
 				interrupts = <5 2 0 2>;
 				interrupt-parent = <&PIC>;
-				reg = <930 20>;
+				reg = <0x930 0x20>;
 				compatible = "fsl,mpc885-cpm-pic",
 				             "fsl,cpm1-pic";
 			};
@@ -178,11 +179,11 @@
 				device_type = "serial";
 				compatible = "fsl,mpc885-smc-uart",
 				             "fsl,cpm1-smc-uart";
-				reg = <a80 10 3e80 40>;
+				reg = <0xa80 0x10 0x3e80 0x40>;
 				interrupts = <4>;
 				interrupt-parent = <&CPM_PIC>;
 				fsl,cpm-brg = <1>;
-				fsl,cpm-command = <0090>;
+				fsl,cpm-command = <0x90>;
 				linux,planetcore-label = "SMC1";
 			};
 
@@ -191,11 +192,11 @@
 				device_type = "serial";
 				compatible = "fsl,mpc885-scc-uart",
 				             "fsl,cpm1-scc-uart";
-				reg = <a20 20 3d00 80>;
-				interrupts = <1d>;
+				reg = <0xa20 0x20 0x3d00 0x80>;
+				interrupts = <29>;
 				interrupt-parent = <&CPM_PIC>;
 				fsl,cpm-brg = <2>;
-				fsl,cpm-command = <0040>;
+				fsl,cpm-command = <0x40>;
 				linux,planetcore-label = "SCC2";
 			};
 
@@ -204,9 +205,9 @@
 				#size-cells = <0>;
 				compatible = "fsl,mpc885-usb",
 				             "fsl,cpm1-usb";
-				reg = <a00 18 1c00 80>;
+				reg = <0xa00 0x18 0x1c00 0x80>;
 				interrupt-parent = <&CPM_PIC>;
-				interrupts = <1e>;
+				interrupts = <30>;
 				fsl,cpm-command = <0000>;
 			};
 		};

arch/powerpc/boot/dts/glacier.dts

@@ -0,0 +1,467 @@
+/*
+ * Device Tree Source for AMCC Glacier (460GT)
+ *
+ * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without
+ * any warranty of any kind, whether express or implied.
+ */
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <1>;
+	model = "amcc,glacier";
+	compatible = "amcc,glacier", "amcc,canyonlands";
+	dcr-parent = <&/cpus/cpu@0>;
+
+	aliases {
+		ethernet0 = &EMAC0;
+		ethernet1 = &EMAC1;
+		ethernet2 = &EMAC2;
+		ethernet3 = &EMAC3;
+		serial0 = &UART0;
+		serial1 = &UART1;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			model = "PowerPC,460GT";
+			reg = <0>;
+			clock-frequency = <0>; /* Filled in by U-Boot */
+			timebase-frequency = <0>; /* Filled in by U-Boot */
+			i-cache-line-size = <20>;
+			d-cache-line-size = <20>;
+			i-cache-size = <8000>;
+			d-cache-size = <8000>;
+			dcr-controller;
+			dcr-access-method = "native";
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0 0 0>; /* Filled in by U-Boot */
+	};
+
+	UIC0: interrupt-controller0 {
+		compatible = "ibm,uic-460gt","ibm,uic";
+		interrupt-controller;
+		cell-index = <0>;
+		dcr-reg = <0c0 009>;
+		#address-cells = <0>;
+		#size-cells = <0>;
+		#interrupt-cells = <2>;
+	};
+
+	UIC1: interrupt-controller1 {
+		compatible = "ibm,uic-460gt","ibm,uic";
+		interrupt-controller;
+		cell-index = <1>;
+		dcr-reg = <0d0 009>;
+		#address-cells = <0>;
+		#size-cells = <0>;
+		#interrupt-cells = <2>;
+		interrupts = <1e 4 1f 4>; /* cascade */
+		interrupt-parent = <&UIC0>;
+	};
+
+	UIC2: interrupt-controller2 {
+		compatible = "ibm,uic-460gt","ibm,uic";
+		interrupt-controller;
+		cell-index = <2>;
+		dcr-reg = <0e0 009>;
+		#address-cells = <0>;
+		#size-cells = <0>;
+		#interrupt-cells = <2>;
+		interrupts = <a 4 b 4>; /* cascade */
+		interrupt-parent = <&UIC0>;
+	};
+
+	UIC3: interrupt-controller3 {
+		compatible = "ibm,uic-460gt","ibm,uic";
+		interrupt-controller;
+		cell-index = <3>;
+		dcr-reg = <0f0 009>;
+		#address-cells = <0>;
+		#size-cells = <0>;
+		#interrupt-cells = <2>;
+		interrupts = <10 4 11 4>; /* cascade */
+		interrupt-parent = <&UIC0>;
+	};
+
+	SDR0: sdr {
+		compatible = "ibm,sdr-460gt";
+		dcr-reg = <00e 002>;
+	};
+
+	CPR0: cpr {
+		compatible = "ibm,cpr-460gt";
+		dcr-reg = <00c 002>;
+	};
+
+	plb {
+		compatible = "ibm,plb-460gt", "ibm,plb4";
+		#address-cells = <2>;
+		#size-cells = <1>;
+		ranges;
+		clock-frequency = <0>; /* Filled in by U-Boot */
+
+		SDRAM0: sdram {
+			compatible = "ibm,sdram-460gt", "ibm,sdram-405gp";
+			dcr-reg = <010 2>;
+		};
+
+		MAL0: mcmal {
+			compatible = "ibm,mcmal-460gt", "ibm,mcmal2";
+			dcr-reg = <180 62>;
+			num-tx-chans = <4>;
+			num-rx-chans = <20>;
+			#address-cells = <0>;
+			#size-cells = <0>;
+			interrupt-parent = <&UIC2>;
+			interrupts = <	/*TXEOB*/ 6 4
+					/*RXEOB*/ 7 4
+					/*SERR*/  3 4
+					/*TXDE*/  4 4
+					/*RXDE*/  5 4>;
+			desc-base-addr-high = <8>;
+		};
+
+		POB0: opb {
+			compatible = "ibm,opb-460gt", "ibm,opb";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <b0000000 4 b0000000 50000000>;
+			clock-frequency = <0>; /* Filled in by U-Boot */
+
+			EBC0: ebc {
+				compatible = "ibm,ebc-460gt", "ibm,ebc";
+				dcr-reg = <012 2>;
+				#address-cells = <2>;
+				#size-cells = <1>;
+				clock-frequency = <0>; /* Filled in by U-Boot */
+				interrupts = <6 4>;
+				interrupt-parent = <&UIC1>;
+			};
+
+			UART0: serial@ef600300 {
+				device_type = "serial";
+				compatible = "ns16550";
+				reg = <ef600300 8>;
+				virtual-reg = <ef600300>;
+				clock-frequency = <0>; /* Filled in by U-Boot */
+				current-speed = <0>; /* Filled in by U-Boot */
+				interrupt-parent = <&UIC1>;
+				interrupts = <1 4>;
+			};
+
+			UART1: serial@ef600400 {
+				device_type = "serial";
+				compatible = "ns16550";
+				reg = <ef600400 8>;
+				virtual-reg = <ef600400>;
+				clock-frequency = <0>; /* Filled in by U-Boot */
+				current-speed = <0>; /* Filled in by U-Boot */
+				interrupt-parent = <&UIC0>;
+				interrupts = <1 4>;
+			};
+
+			UART2: serial@ef600500 {
+				device_type = "serial";
+				compatible = "ns16550";
+				reg = <ef600500 8>;
+				virtual-reg = <ef600500>;
+				clock-frequency = <0>; /* Filled in by U-Boot */
+				current-speed = <0>; /* Filled in by U-Boot */
+				interrupt-parent = <&UIC1>;
+				interrupts = <1d 4>;
+			};
+
+			UART3: serial@ef600600 {
+				device_type = "serial";
+				compatible = "ns16550";
+				reg = <ef600600 8>;
+				virtual-reg = <ef600600>;
+				clock-frequency = <0>; /* Filled in by U-Boot */
+				current-speed = <0>; /* Filled in by U-Boot */
+				interrupt-parent = <&UIC1>;
+				interrupts = <1e 4>;
+			};
+
+			IIC0: i2c@ef600700 {
+				compatible = "ibm,iic-460gt", "ibm,iic";
+				reg = <ef600700 14>;
+				interrupt-parent = <&UIC0>;
+				interrupts = <2 4>;
+			};
+
+			IIC1: i2c@ef600800 {
+				compatible = "ibm,iic-460gt", "ibm,iic";
+				reg = <ef600800 14>;
+				interrupt-parent = <&UIC0>;
+				interrupts = <3 4>;
+			};
+
+			ZMII0: emac-zmii@ef600d00 {
+				compatible = "ibm,zmii-460gt", "ibm,zmii";
+				reg = <ef600d00 c>;
+			};
+
+			RGMII0: emac-rgmii@ef601500 {
+				compatible = "ibm,rgmii-460gt", "ibm,rgmii";
+				reg = <ef601500 8>;
+				has-mdio;
+			};
+
+			RGMII1: emac-rgmii@ef601600 {
+				compatible = "ibm,rgmii-460gt", "ibm,rgmii";
+				reg = <ef601600 8>;
+				has-mdio;
+			};
+
+			TAH0: emac-tah@ef601350 {
+				compatible = "ibm,tah-460gt", "ibm,tah";
+				reg = <ef601350 30>;
+			};
+
+			TAH1: emac-tah@ef601450 {
+				compatible = "ibm,tah-460gt", "ibm,tah";
+				reg = <ef601450 30>;
+			};
+
+			EMAC0: ethernet@ef600e00 {
+				device_type = "network";
+				compatible = "ibm,emac-460gt", "ibm,emac4";
+				interrupt-parent = <&EMAC0>;
+				interrupts = <0 1>;
+				#interrupt-cells = <1>;
+				#address-cells = <0>;
+				#size-cells = <0>;
+				interrupt-map = </*Status*/ 0 &UIC2 10 4
+						 /*Wake*/   1 &UIC2 14 4>;
+				reg = <ef600e00 70>;
+				local-mac-address = [000000000000]; /* Filled in by U-Boot */
+				mal-device = <&MAL0>;
+				mal-tx-channel = <0>;
+				mal-rx-channel = <0>;
+				cell-index = <0>;
+				max-frame-size = <2328>;
+				rx-fifo-size = <1000>;
+				tx-fifo-size = <800>;
+				phy-mode = "rgmii";
+				phy-map = <00000000>;
+				rgmii-device = <&RGMII0>;
+				rgmii-channel = <0>;
+				tah-device = <&TAH0>;
+				tah-channel = <0>;
+				has-inverted-stacr-oc;
+				has-new-stacr-staopc;
+			};
+
+			EMAC1: ethernet@ef600f00 {
+				device_type = "network";
+				compatible = "ibm,emac-460gt", "ibm,emac4";
+				interrupt-parent = <&EMAC1>;
+				interrupts = <0 1>;
+				#interrupt-cells = <1>;
+				#address-cells = <0>;
+				#size-cells = <0>;
+				interrupt-map = </*Status*/ 0 &UIC2 11 4
+						 /*Wake*/   1 &UIC2 15 4>;
+				reg = <ef600f00 70>;
+				local-mac-address = [000000000000]; /* Filled in by U-Boot */
+				mal-device = <&MAL0>;
+				mal-tx-channel = <1>;
+				mal-rx-channel = <8>;
+				cell-index = <1>;
+				max-frame-size = <2328>;
+				rx-fifo-size = <1000>;
+				tx-fifo-size = <800>;
+				phy-mode = "rgmii";
+				phy-map = <00000000>;
+				rgmii-device = <&RGMII0>;
+				rgmii-channel = <1>;
+				tah-device = <&TAH1>;
+				tah-channel = <1>;
+				has-inverted-stacr-oc;
+				has-new-stacr-staopc;
+				mdio-device = <&EMAC0>;
+			};
+
+			EMAC2: ethernet@ef601100 {
+				device_type = "network";
+				compatible = "ibm,emac-460gt", "ibm,emac4";
+				interrupt-parent = <&EMAC2>;
+				interrupts = <0 1>;
+				#interrupt-cells = <1>;
+				#address-cells = <0>;
+				#size-cells = <0>;
+				interrupt-map = </*Status*/ 0 &UIC2 12 4
+						 /*Wake*/   1 &UIC2 16 4>;
+				reg = <ef601100 70>;
+				local-mac-address = [000000000000]; /* Filled in by U-Boot */
+				mal-device = <&MAL0>;
+				mal-tx-channel = <2>;
+				mal-rx-channel = <10>;
+				cell-index = <2>;
+				max-frame-size = <2328>;
+				rx-fifo-size = <1000>;
+				tx-fifo-size = <800>;
+				phy-mode = "rgmii";
+				phy-map = <00000000>;
+				rgmii-device = <&RGMII1>;
+				rgmii-channel = <0>;
+				has-inverted-stacr-oc;
+				has-new-stacr-staopc;
+				mdio-device = <&EMAC0>;
+			};
+
+			EMAC3: ethernet@ef601200 {
+				device_type = "network";
+				compatible = "ibm,emac-460gt", "ibm,emac4";
+				interrupt-parent = <&EMAC3>;
+				interrupts = <0 1>;
+				#interrupt-cells = <1>;
+				#address-cells = <0>;
+				#size-cells = <0>;
+				interrupt-map = </*Status*/ 0 &UIC2 13 4
+						 /*Wake*/   1 &UIC2 17 4>;
+				reg = <ef601200 70>;
+				local-mac-address = [000000000000]; /* Filled in by U-Boot */
+				mal-device = <&MAL0>;
+				mal-tx-channel = <3>;
+				mal-rx-channel = <18>;
+				cell-index = <3>;
+				max-frame-size = <2328>;
+				rx-fifo-size = <1000>;
+				tx-fifo-size = <800>;
+				phy-mode = "rgmii";
+				phy-map = <00000000>;
+				rgmii-device = <&RGMII1>;
+				rgmii-channel = <1>;
+				has-inverted-stacr-oc;
+				has-new-stacr-staopc;
+				mdio-device = <&EMAC0>;
+			};
+		};
+
+		PCIX0: pci@c0ec00000 {
+			device_type = "pci";
+			#interrupt-cells = <1>;
+			#size-cells = <2>;
+			#address-cells = <3>;
+			compatible = "ibm,plb-pcix-460gt", "ibm,plb-pcix";
+			primary;
+			large-inbound-windows;
+			enable-msi-hole;
+			reg = <c 0ec00000   8	/* Config space access */
+			       0 0 0		/* no IACK cycles */
+			       c 0ed00000   4   /* Special cycles */
+			       c 0ec80000 100	/* Internal registers */
+			       c 0ec80100  fc>;	/* Internal messaging registers */
+
+			/* Outbound ranges, one memory and one IO,
+			 * later cannot be changed
+			 */
+			ranges = <02000000 0 80000000 0000000d 80000000 0 80000000
+				  01000000 0 00000000 0000000c 08000000 0 00010000>;
+
+			/* Inbound 2GB range starting at 0 */
+			dma-ranges = <42000000 0 0 0 0 0 80000000>;
+
+			/* This drives busses 0 to 0x3f */
+			bus-range = <0 3f>;
+
+			/* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */
+			interrupt-map-mask = <0000 0 0 0>;
+			interrupt-map = < 0000 0 0 0 &UIC1 0 8 >;
+		};
+
+		PCIE0: pciex@d00000000 {
+			device_type = "pci";
+			#interrupt-cells = <1>;
+			#size-cells = <2>;
+			#address-cells = <3>;
+			compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
+			primary;
+			port = <0>; /* port number */
+			reg = <d 00000000 20000000	/* Config space access */
+			       c 08010000 00001000>;	/* Registers */
+			dcr-reg = <100 020>;
+			sdr-base = <300>;
+
+			/* Outbound ranges, one memory and one IO,
+			 * later cannot be changed
+			 */
+			ranges = <02000000 0 80000000 0000000e 00000000 0 80000000
+				  01000000 0 00000000 0000000f 80000000 0 00010000>;
+
+			/* Inbound 2GB range starting at 0 */
+			dma-ranges = <42000000 0 0 0 0 0 80000000>;
+
+			/* This drives busses 40 to 0x7f */
+			bus-range = <40 7f>;
+
+			/* Legacy interrupts (note the weird polarity, the bridge seems
+			 * to invert PCIe legacy interrupts).
+			 * We are de-swizzling here because the numbers are actually for
+			 * port of the root complex virtual P2P bridge. But I want
+			 * to avoid putting a node for it in the tree, so the numbers
+			 * below are basically de-swizzled numbers.
+			 * The real slot is on idsel 0, so the swizzling is 1:1
+			 */
+			interrupt-map-mask = <0000 0 0 7>;
+			interrupt-map = <
+				0000 0 0 1 &UIC3 c 4 /* swizzled int A */
+				0000 0 0 2 &UIC3 d 4 /* swizzled int B */
+				0000 0 0 3 &UIC3 e 4 /* swizzled int C */
+				0000 0 0 4 &UIC3 f 4 /* swizzled int D */>;
+		};
+
+		PCIE1: pciex@d20000000 {
+			device_type = "pci";
+			#interrupt-cells = <1>;
+			#size-cells = <2>;
+			#address-cells = <3>;
+			compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
+			primary;
+			port = <1>; /* port number */
+			reg = <d 20000000 20000000	/* Config space access */
+			       c 08011000 00001000>;	/* Registers */
+			dcr-reg = <120 020>;
+			sdr-base = <340>;
+
+			/* Outbound ranges, one memory and one IO,
+			 * later cannot be changed
+			 */
+			ranges = <02000000 0 80000000 0000000e 80000000 0 80000000
+				  01000000 0 00000000 0000000f 80010000 0 00010000>;
+
+			/* Inbound 2GB range starting at 0 */
+			dma-ranges = <42000000 0 0 0 0 0 80000000>;
+
+			/* This drives busses 80 to 0xbf */
+			bus-range = <80 bf>;
+
+			/* Legacy interrupts (note the weird polarity, the bridge seems
+			 * to invert PCIe legacy interrupts).
+			 * We are de-swizzling here because the numbers are actually for
+			 * port of the root complex virtual P2P bridge. But I want
+			 * to avoid putting a node for it in the tree, so the numbers
+			 * below are basically de-swizzled numbers.
+			 * The real slot is on idsel 0, so the swizzling is 1:1
+			 */
+			interrupt-map-mask = <0000 0 0 7>;
+			interrupt-map = <
+				0000 0 0 1 &UIC3 10 4 /* swizzled int A */
+				0000 0 0 2 &UIC3 11 4 /* swizzled int B */
+				0000 0 0 3 &UIC3 12 4 /* swizzled int C */
+				0000 0 0 4 &UIC3 13 4 /* swizzled int D */>;
+		};
+	};
+};

arch/powerpc/boot/dts/haleakala.dts

@@ -12,7 +12,7 @@
 	#address-cells = <1>;
 	#size-cells = <1>;
 	model = "amcc,haleakala";
-	compatible = "amcc,kilauea";
+	compatible = "amcc,haleakala", "amcc,kilauea";
 	dcr-parent = <&/cpus/cpu@0>;
 
 	aliases {
@@ -218,7 +218,7 @@
 				mal-tx-channel = <0>;
 				mal-rx-channel = <0>;
 				cell-index = <0>;
-				max-frame-size = <5dc>;
+				max-frame-size = <2328>;
 				rx-fifo-size = <1000>;
 				tx-fifo-size = <800>;
 				phy-mode = "rgmii";

arch/powerpc/boot/dts/katmai.dts

@@ -212,7 +212,7 @@
 				mal-tx-channel = <0>;
 				mal-rx-channel = <0>;
 				cell-index = <0>;
-				max-frame-size = <5dc>;
+				max-frame-size = <2328>;
 				rx-fifo-size = <1000>;
 				tx-fifo-size = <800>;
 				phy-mode = "gmii";

arch/powerpc/boot/dts/kilauea.dts

@@ -219,7 +219,7 @@
 				mal-tx-channel = <0>;
 				mal-rx-channel = <0>;
 				cell-index = <0>;
-				max-frame-size = <5dc>;
+				max-frame-size = <2328>;
 				rx-fifo-size = <1000>;
 				tx-fifo-size = <800>;
 				phy-mode = "rgmii";
@@ -247,7 +247,7 @@
 				mal-tx-channel = <1>;
 				mal-rx-channel = <1>;
 				cell-index = <1>;
-				max-frame-size = <5dc>;
+				max-frame-size = <2328>;
 				rx-fifo-size = <1000>;
 				tx-fifo-size = <800>;
 				phy-mode = "rgmii";

arch/powerpc/boot/dts/ksi8560.dts

@@ -0,0 +1,267 @@
+/*
+ * Device Tree Source for Emerson KSI8560
+ *
+ * Author: Alexandr Smirnov <asmirnov@ru.mvista.com>
+ *
+ * Based on mpc8560ads.dts
+ *
+ * 2008 (c) MontaVista, Software, Inc.  This file is licensed under
+ * the terms of the GNU General Public License version 2.  This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ */
+
+/dts-v1/;
+
+/ {
+	model = "KSI8560";
+	compatible = "emerson,KSI8560";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	aliases {
+		ethernet0 = &enet0;
+		ethernet1 = &enet1;
+		ethernet2 = &enet2;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		PowerPC,8560@0 {
+			device_type = "cpu";
+			reg = <0>;
+			d-cache-line-size = <32>;
+			i-cache-line-size = <32>;
+			d-cache-size = <0x8000>;		/* L1, 32K */
+			i-cache-size = <0x8000>;		/* L1, 32K */
+			timebase-frequency = <0>;		/* From U-boot */
+			bus-frequency = <0>;			/* From U-boot */
+			clock-frequency = <0>;			/* From U-boot */
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x10000000>;			/* Fixed by bootwrapper */
+	};
+
+	soc@fdf00000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		device_type = "soc";
+		ranges = <0x00000000 0xfdf00000 0x00100000>;
+		bus-frequency = <0>;				/* Fixed by bootwrapper */
+
+		memory-controller@2000 {
+			compatible = "fsl,8540-memory-controller";
+			reg = <0x2000 0x1000>;
+			interrupt-parent = <&MPIC>;
+			interrupts = <0x12 0x2>;
+		};
+
+		l2-cache-controller@20000 {
+			compatible = "fsl,8540-l2-cache-controller";
+			reg = <0x20000 0x1000>;
+			cache-line-size = <0x20>;		/* 32 bytes */
+			cache-size = <0x40000>;			/* L2, 256K */
+			interrupt-parent = <&MPIC>;
+			interrupts = <0x10 0x2>;
+		};
+
+		i2c@3000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			cell-index = <0>;
+			compatible = "fsl-i2c";
+			reg = <0x3000 0x100>;
+			interrupts = <0x2b 0x2>;
+			interrupt-parent = <&MPIC>;
+			dfsrr;
+		};
+
+		mdio@24520 {					/* For TSECs */
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "fsl,gianfar-mdio";
+			reg = <0x24520 0x20>;
+
+			PHY1: ethernet-phy@1 {
+				interrupt-parent = <&MPIC>;
+				reg = <0x1>;
+				device_type = "ethernet-phy";
+			};
+
+			PHY2: ethernet-phy@2 {
+				interrupt-parent = <&MPIC>;
+				reg = <0x2>;
+				device_type = "ethernet-phy";
+			};
+		};
+
+		enet0: ethernet@24000 {
+			device_type = "network";
+			model = "TSEC";
+			compatible = "gianfar";
+			reg = <0x24000 0x1000>;
+			/* Mac address filled in by bootwrapper */
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
+			interrupt-parent = <&MPIC>;
+			phy-handle = <&PHY1>;
+		};
+
+		enet1: ethernet@25000 {
+			device_type = "network";
+			model = "TSEC";
+			compatible = "gianfar";
+			reg = <0x25000 0x1000>;
+			/* Mac address filled in by bootwrapper */
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			interrupts = <0x23 0x2 0x24 0x2 0x28 0x2>;
+			interrupt-parent = <&MPIC>;
+			phy-handle = <&PHY2>;
+		};
+
+		MPIC: pic@40000 {
+			#address-cells = <0>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			reg = <0x40000 0x40000>;
+			device_type = "open-pic";
+		};
+
+		cpm@919c0 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "fsl,mpc8560-cpm", "fsl,cpm2";
+			reg = <0x919c0 0x30>;
+			ranges;
+
+			muram@80000 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0x80000 0x10000>;
+
+				data@0 {
+					compatible = "fsl,cpm-muram-data";
+					reg = <0x0 0x4000 0x9000 0x2000>;
+				};
+			};
+
+			brg@919f0 {
+				compatible = "fsl,mpc8560-brg",
+					     "fsl,cpm2-brg",
+					     "fsl,cpm-brg";
+				reg = <0x919f0 0x10 0x915f0 0x10>;
+				clock-frequency = <165000000>;	/* 166MHz */
+			};
+
+			CPMPIC: pic@90c00 {
+				#address-cells = <0>;
+				#interrupt-cells = <2>;
+				interrupt-controller;
+				interrupts = <0x2e 0x2>;
+				interrupt-parent = <&MPIC>;
+				reg = <0x90c00 0x80>;
+				compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
+			};
+
+			serial@91a00 {
+				device_type = "serial";
+				compatible = "fsl,mpc8560-scc-uart",
+					     "fsl,cpm2-scc-uart";
+				reg = <0x91a00 0x20 0x88000 0x100>;
+				fsl,cpm-brg = <1>;
+				fsl,cpm-command = <0x800000>;
+				current-speed = <0x1c200>;
+				interrupts = <0x28 0x8>;
+				interrupt-parent = <&CPMPIC>;
+			};
+
+			serial@91a20 {
+				device_type = "serial";
+				compatible = "fsl,mpc8560-scc-uart",
+					     "fsl,cpm2-scc-uart";
+				reg = <0x91a20 0x20 0x88100 0x100>;
+				fsl,cpm-brg = <2>;
+				fsl,cpm-command = <0x4a00000>;
+				current-speed = <0x1c200>;
+				interrupts = <0x29 0x8>;
+				interrupt-parent = <&CPMPIC>;
+			};
+
+			mdio@90d00 {				/* For FCCs */
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,cpm2-mdio-bitbang";
+				reg = <0x90d00 0x14>;
+				fsl,mdio-pin = <24>;
+				fsl,mdc-pin = <25>;
+
+				PHY0: ethernet-phy@0 {
+					interrupt-parent = <&MPIC>;
+					reg = <0x0>;
+					device_type = "ethernet-phy";
+				};
+			};
+
+			enet2: ethernet@91300 {
+				device_type = "network";
+				compatible = "fsl,mpc8560-fcc-enet",
+					     "fsl,cpm2-fcc-enet";
+				reg = <0x91300 0x20 0x88400 0x100 0x91390 0x1>;
+				/* Mac address filled in by bootwrapper */
+				local-mac-address = [ 00 00 00 00 00 00 ];
+				fsl,cpm-command = <0x12000300>;
+				interrupts = <0x20 0x8>;
+				interrupt-parent = <&CPMPIC>;
+				phy-handle = <&PHY0>;
+			};
+		};
+	};
+
+	localbus@fdf05000 {
+		#address-cells = <2>;
+		#size-cells = <1>;
+		compatible = "fsl,mpc8560-localbus";
+		reg = <0xfdf05000 0x68>;
+
+		ranges = <0x0 0x0 0xe0000000 0x00800000
+			  0x4 0x0 0xe8080000 0x00080000>;
+
+		flash@0,0 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "jedec-flash";
+			reg = <0x0 0x0 0x800000>;
+			bank-width = <0x2>;
+
+			partition@0 {
+				label = "Primary Kernel";
+				reg = <0x0 0x180000>;
+			};
+			partition@180000 {
+				label = "Primary Filesystem";
+				reg = <0x180000 0x580000>;
+			};
+			partition@700000 {
+				label = "Monitor";
+				reg = <0x300000 0x100000>;
+				read-only;
+			};
+		};
+
+		cpld@4,0 {
+			compatible = "emerson,KSI8560-cpld";
+			reg = <0x4 0x0 0x80000>;
+		};
+	};
+
+
+	chosen {
+		linux,stdout-path = "/soc/cpm/serial@91a00";
+	};
+};

arch/powerpc/boot/dts/kuroboxHD.dts

@@ -7,6 +7,7 @@
  * Based on sandpoint.dts
  *
  * 2006 (c) G. Liakhovetski <g.liakhovetski@gmx.de>
+ * Copyright 2008 Freescale Semiconductor, Inc.
  *
  * This file is licensed under
  * the terms of the GNU General Public License version 2.  This program
@@ -17,6 +18,8 @@ XXXX add flash parts, rtc, ??
 
  */
 
+/dts-v1/;
+
 / {
 	model = "KuroboxHD";
 	compatible = "linkstation";
@@ -35,19 +38,19 @@ XXXX add flash parts, rtc, ??
 
 		PowerPC,603e { /* Really 8241 */
 			device_type = "cpu";
-			reg = <0>;
-			clock-frequency = <bebc200>;	/* Fixed by bootloader */
-			timebase-frequency = <1743000>; /* Fixed by bootloader */
+			reg = <0x0>;
+			clock-frequency = <200000000>;	/* Fixed by bootloader */
+			timebase-frequency = <24391680>; /* Fixed by bootloader */
 			bus-frequency = <0>;		/* Fixed by bootloader */
 			/* Following required by dtc but not used */
-			i-cache-size = <4000>;
-			d-cache-size = <4000>;
+			i-cache-size = <0x4000>;
+			d-cache-size = <0x4000>;
 		};
 	};
 
 	memory {
 		device_type = "memory";
-		reg = <00000000 04000000>;
+		reg = <0x0 0x4000000>;
 	};
 
 	soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */
@@ -56,26 +59,26 @@ XXXX add flash parts, rtc, ??
 		device_type = "soc";
 		compatible = "mpc10x";
 		store-gathering = <0>; /* 0 == off, !0 == on */
-		reg = <80000000 00100000>;
-		ranges = <80000000 80000000 70000000	/* pci mem space */
-			  fc000000 fc000000 00100000	/* EUMB */
-			  fe000000 fe000000 00c00000	/* pci i/o space */
-			  fec00000 fec00000 00300000	/* pci cfg regs */
-			  fef00000 fef00000 00100000>;	/* pci iack */
+		reg = <0x80000000 0x100000>;
+		ranges = <0x80000000 0x80000000 0x70000000	/* pci mem space */
+			  0xfc000000 0xfc000000 0x100000	/* EUMB */
+			  0xfe000000 0xfe000000 0xc00000	/* pci i/o space */
+			  0xfec00000 0xfec00000 0x300000	/* pci cfg regs */
+			  0xfef00000 0xfef00000 0x100000>;	/* pci iack */
 
 		i2c@80003000 {
 			#address-cells = <1>;
 			#size-cells = <0>;
 			cell-index = <0>;
 			compatible = "fsl-i2c";
-			reg = <80003000 1000>;
+			reg = <0x80003000 0x1000>;
 			interrupts = <5 2>;
 			interrupt-parent = <&mpic>;
 
 			rtc@32 {
 				device_type = "rtc";
 				compatible = "ricoh,rs5c372a";
-				reg = <32>;
+				reg = <0x32>;
 			};
 		};
 
@@ -83,9 +86,9 @@ XXXX add flash parts, rtc, ??
 			cell-index = <0>;
 			device_type = "serial";
 			compatible = "ns16550";
-			reg = <80004500 8>;
-			clock-frequency = <5d08d88>;
-			current-speed = <2580>;
+			reg = <0x80004500 0x8>;
+			clock-frequency = <97553800>;
+			current-speed = <9600>;
 			interrupts = <9 0>;
 			interrupt-parent = <&mpic>;
 		};
@@ -94,10 +97,10 @@ XXXX add flash parts, rtc, ??
 			cell-index = <1>;
 			device_type = "serial";
 			compatible = "ns16550";
-			reg = <80004600 8>;
-			clock-frequency = <5d08d88>;
-			current-speed = <e100>;
-			interrupts = <a 0>;
+			reg = <0x80004600 0x8>;
+			clock-frequency = <97553800>;
+			current-speed = <57600>;
+			interrupts = <10 0>;
 			interrupt-parent = <&mpic>;
 		};
 
@@ -107,7 +110,7 @@ XXXX add flash parts, rtc, ??
 			device_type = "open-pic";
 			compatible = "chrp,open-pic";
 			interrupt-controller;
-			reg = <80040000 40000>;
+			reg = <0x80040000 0x40000>;
 		};
 
 		pci0: pci@fec00000 {
@@ -116,29 +119,29 @@ XXXX add flash parts, rtc, ??
 			#interrupt-cells = <1>;
 			device_type = "pci";
 			compatible = "mpc10x-pci";
-			reg = <fec00000 400000>;
-			ranges = <01000000 0        0 fe000000 0 00c00000
-				  02000000 0 80000000 80000000 0 70000000>;
-			bus-range = <0 ff>;
-			clock-frequency = <7f28155>;
+			reg = <0xfec00000 0x400000>;
+			ranges = <0x1000000 0x0        0x0 0xfe000000 0x0 0xc00000
+				  0x2000000 0x0 0x80000000 0x80000000 0x0 0x70000000>;
+			bus-range = <0 255>;
+			clock-frequency = <133333333>;
 			interrupt-parent = <&mpic>;
-			interrupt-map-mask = <f800 0 0 7>;
+			interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 			interrupt-map = <
 				/* IDSEL 11 - IRQ0 ETH */
-				5800 0 0 1 &mpic 0 1
-				5800 0 0 2 &mpic 1 1
-				5800 0 0 3 &mpic 2 1
-				5800 0 0 4 &mpic 3 1
+				0x5800 0x0 0x0 0x1 &mpic 0x0 0x1
+				0x5800 0x0 0x0 0x2 &mpic 0x1 0x1
+				0x5800 0x0 0x0 0x3 &mpic 0x2 0x1
+				0x5800 0x0 0x0 0x4 &mpic 0x3 0x1
 				/* IDSEL 12 - IRQ1 IDE0 */
-				6000 0 0 1 &mpic 1 1
-				6000 0 0 2 &mpic 2 1
-				6000 0 0 3 &mpic 3 1
-				6000 0 0 4 &mpic 0 1
+				0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
+				0x6000 0x0 0x0 0x2 &mpic 0x2 0x1
+				0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
+				0x6000 0x0 0x0 0x4 &mpic 0x0 0x1
 				/* IDSEL 14 - IRQ3 USB2.0 */
-				7000 0 0 1 &mpic 3 1
-				7000 0 0 2 &mpic 3 1
-				7000 0 0 3 &mpic 3 1
-				7000 0 0 4 &mpic 3 1
+				0x7000 0x0 0x0 0x1 &mpic 0x3 0x1
+				0x7000 0x0 0x0 0x2 &mpic 0x3 0x1
+				0x7000 0x0 0x0 0x3 &mpic 0x3 0x1
+				0x7000 0x0 0x0 0x4 &mpic 0x3 0x1
 			>;
 		};
 	};

arch/powerpc/boot/dts/kuroboxHG.dts

@@ -7,6 +7,7 @@
  * Based on sandpoint.dts
  *
  * 2006 (c) G. Liakhovetski <g.liakhovetski@gmx.de>
+ * Copyright 2008 Freescale Semiconductor, Inc.
  *
  * This file is licensed under
  * the terms of the GNU General Public License version 2.  This program
@@ -17,6 +18,8 @@ XXXX add flash parts, rtc, ??
 
  */
 
+/dts-v1/;
+
 / {
 	model = "KuroboxHG";
 	compatible = "linkstation";
@@ -35,19 +38,19 @@ XXXX add flash parts, rtc, ??
 
 		PowerPC,603e { /* Really 8241 */
 			device_type = "cpu";
-			reg = <0>;
-			clock-frequency = <fdad680>;	/* Fixed by bootloader */
-			timebase-frequency = <1F04000>; /* Fixed by bootloader */
+			reg = <0x0>;
+			clock-frequency = <266000000>;	/* Fixed by bootloader */
+			timebase-frequency = <32522240>; /* Fixed by bootloader */
 			bus-frequency = <0>;		/* Fixed by bootloader */
 			/* Following required by dtc but not used */
-			i-cache-size = <4000>;
-			d-cache-size = <4000>;
+			i-cache-size = <0x4000>;
+			d-cache-size = <0x4000>;
 		};
 	};
 
 	memory {
 		device_type = "memory";
-		reg = <00000000 08000000>;
+		reg = <0x0 0x8000000>;
 	};
 
 	soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */
@@ -56,26 +59,26 @@ XXXX add flash parts, rtc, ??
 		device_type = "soc";
 		compatible = "mpc10x";
 		store-gathering = <0>; /* 0 == off, !0 == on */
-		reg = <80000000 00100000>;
-		ranges = <80000000 80000000 70000000	/* pci mem space */
-			  fc000000 fc000000 00100000	/* EUMB */
-			  fe000000 fe000000 00c00000	/* pci i/o space */
-			  fec00000 fec00000 00300000	/* pci cfg regs */
-			  fef00000 fef00000 00100000>;	/* pci iack */
+		reg = <0x80000000 0x100000>;
+		ranges = <0x80000000 0x80000000 0x70000000	/* pci mem space */
+			  0xfc000000 0xfc000000 0x100000	/* EUMB */
+			  0xfe000000 0xfe000000 0xc00000	/* pci i/o space */
+			  0xfec00000 0xfec00000 0x300000	/* pci cfg regs */
+			  0xfef00000 0xfef00000 0x100000>;	/* pci iack */
 
 		i2c@80003000 {
 			#address-cells = <1>;
 			#size-cells = <0>;
 			cell-index = <0>;
 			compatible = "fsl-i2c";
-			reg = <80003000 1000>;
+			reg = <0x80003000 0x1000>;
 			interrupts = <5 2>;
 			interrupt-parent = <&mpic>;
 
 			rtc@32 {
 				device_type = "rtc";
 				compatible = "ricoh,rs5c372a";
-				reg = <32>;
+				reg = <0x32>;
 			};
 		};
 
@@ -83,9 +86,9 @@ XXXX add flash parts, rtc, ??
 			cell-index = <0>;
 			device_type = "serial";
 			compatible = "ns16550";
-			reg = <80004500 8>;
-			clock-frequency = <7c044a8>;
-			current-speed = <2580>;
+			reg = <0x80004500 0x8>;
+			clock-frequency = <130041000>;
+			current-speed = <9600>;
 			interrupts = <9 0>;
 			interrupt-parent = <&mpic>;
 		};
@@ -94,10 +97,10 @@ XXXX add flash parts, rtc, ??
 			cell-index = <1>;
 			device_type = "serial";
 			compatible = "ns16550";
-			reg = <80004600 8>;
-			clock-frequency = <7c044a8>;
-			current-speed = <e100>;
-			interrupts = <a 0>;
+			reg = <0x80004600 0x8>;
+			clock-frequency = <130041000>;
+			current-speed = <57600>;
+			interrupts = <10 0>;
 			interrupt-parent = <&mpic>;
 		};
 
@@ -107,7 +110,7 @@ XXXX add flash parts, rtc, ??
 			device_type = "open-pic";
 			compatible = "chrp,open-pic";
 			interrupt-controller;
-			reg = <80040000 40000>;
+			reg = <0x80040000 0x40000>;
 		};
 
 		pci0: pci@fec00000 {
@@ -116,29 +119,29 @@ XXXX add flash parts, rtc, ??
 			#interrupt-cells = <1>;
 			device_type = "pci";
 			compatible = "mpc10x-pci";
-			reg = <fec00000 400000>;
-			ranges = <01000000 0        0 fe000000 0 00c00000
-				  02000000 0 80000000 80000000 0 70000000>;
-			bus-range = <0 ff>;
-			clock-frequency = <7f28155>;
+			reg = <0xfec00000 0x400000>;
+			ranges = <0x1000000 0x0        0x0 0xfe000000 0x0 0xc00000
+				  0x2000000 0x0 0x80000000 0x80000000 0x0 0x70000000>;
+			bus-range = <0 255>;
+			clock-frequency = <133333333>;
 			interrupt-parent = <&mpic>;
-			interrupt-map-mask = <f800 0 0 7>;
+			interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 			interrupt-map = <
 				/* IDSEL 11 - IRQ0 ETH */
-				5800 0 0 1 &mpic 0 1
-				5800 0 0 2 &mpic 1 1
-				5800 0 0 3 &mpic 2 1
-				5800 0 0 4 &mpic 3 1
+				0x5800 0x0 0x0 0x1 &mpic 0x0 0x1
+				0x5800 0x0 0x0 0x2 &mpic 0x1 0x1
+				0x5800 0x0 0x0 0x3 &mpic 0x2 0x1
+				0x5800 0x0 0x0 0x4 &mpic 0x3 0x1
 				/* IDSEL 12 - IRQ1 IDE0 */
-				6000 0 0 1 &mpic 1 1
-				6000 0 0 2 &mpic 2 1
-				6000 0 0 3 &mpic 3 1
-				6000 0 0 4 &mpic 0 1
+				0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
+				0x6000 0x0 0x0 0x2 &mpic 0x2 0x1
+				0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
+				0x6000 0x0 0x0 0x4 &mpic 0x0 0x1
 				/* IDSEL 14 - IRQ3 USB2.0 */
-				7000 0 0 1 &mpic 3 1
-				7000 0 0 2 &mpic 3 1
-				7000 0 0 3 &mpic 3 1
-				7000 0 0 4 &mpic 3 1
+				0x7000 0x0 0x0 0x1 &mpic 0x3 0x1
+				0x7000 0x0 0x0 0x2 &mpic 0x3 0x1
+				0x7000 0x0 0x0 0x3 &mpic 0x3 0x1
+				0x7000 0x0 0x0 0x4 &mpic 0x3 0x1
 			>;
 		};
 	};

arch/powerpc/boot/dts/makalu.dts

@@ -219,7 +219,7 @@
 				mal-tx-channel = <0>;
 				mal-rx-channel = <0>;
 				cell-index = <0>;
-				max-frame-size = <5dc>;
+				max-frame-size = <2328>;
 				rx-fifo-size = <1000>;
 				tx-fifo-size = <800>;
 				phy-mode = "rgmii";
@@ -247,7 +247,7 @@
 				mal-tx-channel = <1>;
 				mal-rx-channel = <1>;
 				cell-index = <1>;
-				max-frame-size = <5dc>;
+				max-frame-size = <2328>;
 				rx-fifo-size = <1000>;
 				tx-fifo-size = <800>;
 				phy-mode = "rgmii";

arch/powerpc/boot/dts/mpc7448hpc2.dts

@@ -1,7 +1,7 @@
 /*
  * MPC7448HPC2 (Taiga) board Device Tree Source
  *
- * Copyright 2006 Freescale Semiconductor Inc.
+ * Copyright 2006, 2008 Freescale Semiconductor Inc.
  * 2006 Roy Zang <Roy Zang at freescale.com>.
  *
  * This program is free software; you can redistribute  it and/or modify it
@@ -10,6 +10,7 @@
  * option) any later version.
  */
 
+/dts-v1/;
 
 / {
 	model = "mpc7448hpc2";
@@ -23,11 +24,11 @@
 				
 		PowerPC,7448@0 {
 			device_type = "cpu";
-			reg = <0>;
-			d-cache-line-size = <20>;	// 32 bytes
-			i-cache-line-size = <20>;	// 32 bytes
-			d-cache-size = <8000>;		// L1, 32K bytes
-			i-cache-size = <8000>;		// L1, 32K bytes
+			reg = <0x0>;
+			d-cache-line-size = <32>;	// 32 bytes
+			i-cache-line-size = <32>;	// 32 bytes
+			d-cache-size = <0x8000>;		// L1, 32K bytes
+			i-cache-size = <0x8000>;		// L1, 32K bytes
 			timebase-frequency = <0>;	// 33 MHz, from uboot
 			clock-frequency = <0>;		// From U-Boot
 			bus-frequency = <0>;		// From U-Boot
@@ -36,7 +37,7 @@
 
 	memory {
 		device_type = "memory";
-		reg = <00000000 20000000	// DDR2   512M at 0
+		reg = <0x0 0x20000000	// DDR2   512M at 0
 		       >;
 	};
 
@@ -44,14 +45,14 @@
 		#address-cells = <1>;
 		#size-cells = <1>;
 		device_type = "tsi-bridge";
-		ranges = <00000000 c0000000 00010000>;
-		reg = <c0000000 00010000>;
+		ranges = <0x0 0xc0000000 0x10000>;
+		reg = <0xc0000000 0x10000>;
 		bus-frequency = <0>;
 
 		i2c@7000 {
 			interrupt-parent = <&mpic>;
-			interrupts = <E 0>;
-			reg = <7000 400>;
+			interrupts = <14 0>;
+			reg = <0x7000 0x400>;
 			device_type = "i2c";
 			compatible  = "tsi108-i2c";
 		};
@@ -59,20 +60,20 @@
 		MDIO: mdio@6000 {
 			device_type = "mdio";
 			compatible = "tsi108-mdio";
-			reg = <6000 50>;
+			reg = <0x6000 0x50>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 
 			phy8: ethernet-phy@8 {
 				interrupt-parent = <&mpic>;
 				interrupts = <2 1>;
-				reg = <8>;
+				reg = <0x8>;
 			};
 
 			phy9: ethernet-phy@9 {
 				interrupt-parent = <&mpic>;
 				interrupts = <2 1>;
-				reg = <9>;
+				reg = <0x9>;
 			};
 
 		};
@@ -82,9 +83,9 @@
 			#size-cells = <0>;
 			device_type = "network";
 			compatible = "tsi108-ethernet";
-			reg = <6000 200>;
+			reg = <0x6000 0x200>;
 			address = [ 00 06 D2 00 00 01 ];
-			interrupts = <10 2>;
+			interrupts = <16 2>;
 			interrupt-parent = <&mpic>;
 			mdio-handle = <&MDIO>;
 			phy-handle = <&phy8>;
@@ -96,9 +97,9 @@
 			#size-cells = <0>;
 			device_type = "network";
 			compatible = "tsi108-ethernet";
-			reg = <6400 200>;
+			reg = <0x6400 0x200>;
 			address = [ 00 06 D2 00 00 02 ];
-			interrupts = <11 2>;
+			interrupts = <17 2>;
 			interrupt-parent = <&mpic>;
 			mdio-handle = <&MDIO>;
 			phy-handle = <&phy9>;
@@ -107,18 +108,18 @@
 		serial@7808 {
 			device_type = "serial";
 			compatible = "ns16550";
-			reg = <7808 200>;
-			clock-frequency = <3f6b5a00>;
-			interrupts = <c 0>;
+			reg = <0x7808 0x200>;
+			clock-frequency = <1064000000>;
+			interrupts = <12 0>;
 			interrupt-parent = <&mpic>;
 		};
 
 		serial@7c08 {
 			device_type = "serial";
 			compatible = "ns16550";
-			reg = <7c08 200>;
-			clock-frequency = <3f6b5a00>;
-			interrupts = <d 0>;
+			reg = <0x7c08 0x200>;
+			clock-frequency = <1064000000>;
+			interrupts = <13 0>;
 			interrupt-parent = <&mpic>;
 		};
 
@@ -127,7 +128,7 @@
 			interrupt-controller;
 			#address-cells = <0>;
 			#interrupt-cells = <2>;
-			reg = <7400 400>;
+			reg = <0x7400 0x400>;
 			compatible = "chrp,open-pic";
 			device_type = "open-pic";
                        	big-endian;
@@ -138,39 +139,39 @@
 			#interrupt-cells = <1>;
 			#size-cells = <2>;
 			#address-cells = <3>;
-			reg = <1000 1000>;
+			reg = <0x1000 0x1000>;
 			bus-range = <0 0>;
-			ranges = <02000000 0 e0000000 e0000000 0 1A000000	
-				  01000000 0 00000000 fa000000 0 00010000>;
-			clock-frequency = <7f28154>;
+			ranges = <0x2000000 0x0 0xe0000000 0xe0000000 0x0 0x1a000000	
+				  0x1000000 0x0 0x0 0xfa000000 0x0 0x10000>;
+			clock-frequency = <133333332>;
 			interrupt-parent = <&mpic>;
-			interrupts = <17 2>;
-			interrupt-map-mask = <f800 0 0 7>;
+			interrupts = <23 2>;
+			interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 			interrupt-map = <
 
 				/* IDSEL 0x11 */
-				0800 0 0 1 &RT0 24 0
-				0800 0 0 2 &RT0 25 0
-				0800 0 0 3 &RT0 26 0
-				0800 0 0 4 &RT0 27 0
+				0x800 0x0 0x0 0x1 &RT0 0x24 0x0
+				0x800 0x0 0x0 0x2 &RT0 0x25 0x0
+				0x800 0x0 0x0 0x3 &RT0 0x26 0x0
+				0x800 0x0 0x0 0x4 &RT0 0x27 0x0
 
 				/* IDSEL 0x12 */
-				1000 0 0 1 &RT0 25 0
-				1000 0 0 2 &RT0 26 0
-				1000 0 0 3 &RT0 27 0
-				1000 0 0 4 &RT0 24 0
+				0x1000 0x0 0x0 0x1 &RT0 0x25 0x0
+				0x1000 0x0 0x0 0x2 &RT0 0x26 0x0
+				0x1000 0x0 0x0 0x3 &RT0 0x27 0x0
+				0x1000 0x0 0x0 0x4 &RT0 0x24 0x0
 
 				/* IDSEL 0x13 */
-				1800 0 0 1 &RT0 26 0
-				1800 0 0 2 &RT0 27 0
-				1800 0 0 3 &RT0 24 0
-				1800 0 0 4 &RT0 25 0
+				0x1800 0x0 0x0 0x1 &RT0 0x26 0x0
+				0x1800 0x0 0x0 0x2 &RT0 0x27 0x0
+				0x1800 0x0 0x0 0x3 &RT0 0x24 0x0
+				0x1800 0x0 0x0 0x4 &RT0 0x25 0x0
 
 				/* IDSEL 0x14 */
-				2000 0 0 1 &RT0 27 0
-				2000 0 0 2 &RT0 24 0
-				2000 0 0 3 &RT0 25 0
-				2000 0 0 4 &RT0 26 0
+				0x2000 0x0 0x0 0x1 &RT0 0x27 0x0
+				0x2000 0x0 0x0 0x2 &RT0 0x24 0x0
+				0x2000 0x0 0x0 0x3 &RT0 0x25 0x0
+				0x2000 0x0 0x0 0x4 &RT0 0x26 0x0
 				>;
 
 			RT0: router@1180 {
@@ -180,7 +181,7 @@
 				#address-cells = <0>;
 				#interrupt-cells = <2>;
 				big-endian;
-				interrupts = <17 2>;
+				interrupts = <23 2>;
 				interrupt-parent = <&mpic>;
 			};
 		};

arch/powerpc/boot/dts/mpc8272ads.dts

@@ -1,7 +1,7 @@
 /*
  * MPC8272 ADS Device Tree Source
  *
- * Copyright 2005 Freescale Semiconductor Inc.
+ * Copyright 2005,2008 Freescale Semiconductor Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -9,6 +9,8 @@
  * option) any later version.
  */
 
+/dts-v1/;
+
 / {
 	model = "MPC8272ADS";
 	compatible = "fsl,mpc8272ads";
@@ -21,11 +23,11 @@
 
 		PowerPC,8272@0 {
 			device_type = "cpu";
-			reg = <0>;
-			d-cache-line-size = <d#32>;
-			i-cache-line-size = <d#32>;
-			d-cache-size = <d#16384>;
-			i-cache-size = <d#16384>;
+			reg = <0x0>;
+			d-cache-line-size = <32>;
+			i-cache-line-size = <32>;
+			d-cache-size = <16384>;
+			i-cache-size = <16384>;
 			timebase-frequency = <0>;
 			bus-frequency = <0>;
 			clock-frequency = <0>;
@@ -34,7 +36,7 @@
 
 	memory {
 		device_type = "memory";
-		reg = <0 0>;
+		reg = <0x0 0x0>;
 	};
 
 	localbus@f0010100 {
@@ -42,21 +44,21 @@
 		             "fsl,pq2-localbus";
 		#address-cells = <2>;
 		#size-cells = <1>;
-		reg = <f0010100 40>;
+		reg = <0xf0010100 0x40>;
 
-		ranges = <0 0 fe000000 02000000
-		          1 0 f4500000 00008000
-		          3 0 f8200000 00008000>;
+		ranges = <0x0 0x0 0xfe000000 0x2000000
+		          0x1 0x0 0xf4500000 0x8000
+		          0x3 0x0 0xf8200000 0x8000>;
 
 		flash@0,0 {
 			compatible = "jedec-flash";
-			reg = <0 0 2000000>;
+			reg = <0x0 0x0 0x2000000>;
 			bank-width = <4>;
 			device-width = <1>;
 		};
 
 		board-control@1,0 {
-			reg = <1 0 20>;
+			reg = <0x1 0x0 0x20>;
 			compatible = "fsl,mpc8272ads-bcsr";
 		};
 
@@ -65,46 +67,46 @@
 			             "fsl,pq2ads-pci-pic";
 			#interrupt-cells = <1>;
 			interrupt-controller;
-			reg = <3 0 8>;
+			reg = <0x3 0x0 0x8>;
 			interrupt-parent = <&PIC>;
-			interrupts = <14 8>;
+			interrupts = <20 8>;
 		};
 	};
 
 
 	pci@f0010800 {
 		device_type = "pci";
-		reg = <f0010800 10c f00101ac 8 f00101c4 8>;
+		reg = <0xf0010800 0x10c 0xf00101ac 0x8 0xf00101c4 0x8>;
 		compatible = "fsl,mpc8272-pci", "fsl,pq2-pci";
 		#interrupt-cells = <1>;
 		#size-cells = <2>;
 		#address-cells = <3>;
-		clock-frequency = <d#66666666>;
-		interrupt-map-mask = <f800 0 0 7>;
+		clock-frequency = <66666666>;
+		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 		interrupt-map = <
 		                 /* IDSEL 0x16 */
-		                 b000 0 0 1 &PCI_PIC 0
-		                 b000 0 0 2 &PCI_PIC 1
-		                 b000 0 0 3 &PCI_PIC 2
-		                 b000 0 0 4 &PCI_PIC 3
+		                 0xb000 0x0 0x0 0x1 &PCI_PIC 0
+		                 0xb000 0x0 0x0 0x2 &PCI_PIC 1
+		                 0xb000 0x0 0x0 0x3 &PCI_PIC 2
+		                 0xb000 0x0 0x0 0x4 &PCI_PIC 3
 
 		                 /* IDSEL 0x17 */
-		                 b800 0 0 1 &PCI_PIC 4
-		                 b800 0 0 2 &PCI_PIC 5
-		                 b800 0 0 3 &PCI_PIC 6
-		                 b800 0 0 4 &PCI_PIC 7
+		                 0xb800 0x0 0x0 0x1 &PCI_PIC 4
+		                 0xb800 0x0 0x0 0x2 &PCI_PIC 5
+		                 0xb800 0x0 0x0 0x3 &PCI_PIC 6
+		                 0xb800 0x0 0x0 0x4 &PCI_PIC 7
 
 		                 /* IDSEL 0x18 */
-		                 c000 0 0 1 &PCI_PIC 8
-		                 c000 0 0 2 &PCI_PIC 9
-		                 c000 0 0 3 &PCI_PIC a
-		                 c000 0 0 4 &PCI_PIC b>;
+		                 0xc000 0x0 0x0 0x1 &PCI_PIC 8
+		                 0xc000 0x0 0x0 0x2 &PCI_PIC 9
+		                 0xc000 0x0 0x0 0x3 &PCI_PIC 10
+		                 0xc000 0x0 0x0 0x4 &PCI_PIC 11>;
 
 		interrupt-parent = <&PIC>;
-		interrupts = <12 8>;
-		ranges = <42000000 0 80000000 80000000 0 20000000
-		          02000000 0 a0000000 a0000000 0 20000000
-		          01000000 0 00000000 f6000000 0 02000000>;
+		interrupts = <18 8>;
+		ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x20000000
+		          0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
+		          0x1000000 0x0 0x0 0xf6000000 0x0 0x2000000>;
 	};
 
 	soc@f0000000 {
@@ -112,26 +114,26 @@
 		#size-cells = <1>;
 		device_type = "soc";
 		compatible = "fsl,mpc8272", "fsl,pq2-soc";
-		ranges = <00000000 f0000000 00053000>;
+		ranges = <0x0 0xf0000000 0x53000>;
 
 		// Temporary -- will go away once kernel uses ranges for get_immrbase().
-		reg = <f0000000 00053000>;
+		reg = <0xf0000000 0x53000>;
 
 		cpm@119c0 {
 			#address-cells = <1>;
 			#size-cells = <1>;
 			compatible = "fsl,mpc8272-cpm", "fsl,cpm2";
-			reg = <119c0 30>;
+			reg = <0x119c0 0x30>;
 			ranges;
 
 			muram@0 {
 				#address-cells = <1>;
 				#size-cells = <1>;
-				ranges = <0 0 10000>;
+				ranges = <0x0 0x0 0x10000>;
 
 				data@0 {
 					compatible = "fsl,cpm-muram-data";
-					reg = <0 2000 9800 800>;
+					reg = <0x0 0x2000 0x9800 0x800>;
 				};
 			};
 
@@ -139,29 +141,29 @@
 				compatible = "fsl,mpc8272-brg",
 				             "fsl,cpm2-brg",
 				             "fsl,cpm-brg";
-				reg = <119f0 10 115f0 10>;
+				reg = <0x119f0 0x10 0x115f0 0x10>;
 			};
 
 			serial@11a00 {
 				device_type = "serial";
 				compatible = "fsl,mpc8272-scc-uart",
 				             "fsl,cpm2-scc-uart";
-				reg = <11a00 20 8000 100>;
-				interrupts = <28 8>;
+				reg = <0x11a00 0x20 0x8000 0x100>;
+				interrupts = <40 8>;
 				interrupt-parent = <&PIC>;
 				fsl,cpm-brg = <1>;
-				fsl,cpm-command = <00800000>;
+				fsl,cpm-command = <0x800000>;
 			};
 
 			serial@11a60 {
 				device_type = "serial";
 				compatible = "fsl,mpc8272-scc-uart",
 				             "fsl,cpm2-scc-uart";
-				reg = <11a60 20 8300 100>;
-				interrupts = <2b 8>;
+				reg = <0x11a60 0x20 0x8300 0x100>;
+				interrupts = <43 8>;
 				interrupt-parent = <&PIC>;
 				fsl,cpm-brg = <4>;
-				fsl,cpm-command = <0ce00000>;
+				fsl,cpm-command = <0xce00000>;
 			};
 
 			mdio@10d40 {
@@ -169,23 +171,23 @@
 				compatible = "fsl,mpc8272ads-mdio-bitbang",
 				             "fsl,mpc8272-mdio-bitbang",
 				             "fsl,cpm2-mdio-bitbang";
-				reg = <10d40 14>;
+				reg = <0x10d40 0x14>;
 				#address-cells = <1>;
 				#size-cells = <0>;
-				fsl,mdio-pin = <12>;
-				fsl,mdc-pin = <13>;
+				fsl,mdio-pin = <18>;
+				fsl,mdc-pin = <19>;
 
 				PHY0: ethernet-phy@0 {
 					interrupt-parent = <&PIC>;
-					interrupts = <17 8>;
-					reg = <0>;
+					interrupts = <23 8>;
+					reg = <0x0>;
 					device_type = "ethernet-phy";
 				};
 
 				PHY1: ethernet-phy@1 {
 					interrupt-parent = <&PIC>;
-					interrupts = <17 8>;
-					reg = <3>;
+					interrupts = <23 8>;
+					reg = <0x3>;
 					device_type = "ethernet-phy";
 				};
 			};
@@ -194,33 +196,33 @@
 				device_type = "network";
 				compatible = "fsl,mpc8272-fcc-enet",
 				             "fsl,cpm2-fcc-enet";
-				reg = <11300 20 8400 100 11390 1>;
+				reg = <0x11300 0x20 0x8400 0x100 0x11390 0x1>;
 				local-mac-address = [ 00 00 00 00 00 00 ];
-				interrupts = <20 8>;
+				interrupts = <32 8>;
 				interrupt-parent = <&PIC>;
 				phy-handle = <&PHY0>;
 				linux,network-index = <0>;
-				fsl,cpm-command = <12000300>;
+				fsl,cpm-command = <0x12000300>;
 			};
 
 			ethernet@11320 {
 				device_type = "network";
 				compatible = "fsl,mpc8272-fcc-enet",
 				             "fsl,cpm2-fcc-enet";
-				reg = <11320 20 8500 100 113b0 1>;
+				reg = <0x11320 0x20 0x8500 0x100 0x113b0 0x1>;
 				local-mac-address = [ 00 00 00 00 00 00 ];
-				interrupts = <21 8>;
+				interrupts = <33 8>;
 				interrupt-parent = <&PIC>;
 				phy-handle = <&PHY1>;
 				linux,network-index = <1>;
-				fsl,cpm-command = <16200300>;
+				fsl,cpm-command = <0x16200300>;
 			};
 		};
 
 		PIC: interrupt-controller@10c00 {
 			#interrupt-cells = <2>;
 			interrupt-controller;
-			reg = <10c00 80>;
+			reg = <0x10c00 0x80>;
 			compatible = "fsl,mpc8272-pic", "fsl,cpm2-pic";
 		};
 
@@ -232,14 +234,14 @@
 			             "fsl,talitos-sec2",
 			             "fsl,talitos",
 			             "talitos";
-			reg = <30000 10000>;
-			interrupts = <b 8>;
+			reg = <0x30000 0x10000>;
+			interrupts = <11 8>;
 			interrupt-parent = <&PIC>;
 			num-channels = <4>;
-			channel-fifo-len = <18>;
-			exec-units-mask = <0000007e>;
+			channel-fifo-len = <24>;
+			exec-units-mask = <0x7e>;
 /* desc mask is for rev1.x, we need runtime fixup for >=2.x */
-			descriptor-types-mask = <01010ebf>;
+			descriptor-types-mask = <0x1010ebf>;
 		};
 	};
 

arch/powerpc/boot/dts/mpc832x_mds.dts

@@ -255,9 +255,7 @@
 		enet0: ucc@2200 {
 			device_type = "network";
 			compatible = "ucc_geth";
-			model = "UCC";
 			cell-index = <3>;
-			device-id = <3>;
 			reg = <0x2200 0x200>;
 			interrupts = <34>;
 			interrupt-parent = <&qeic>;
@@ -271,9 +269,7 @@
 		enet1: ucc@3200 {
 			device_type = "network";
 			compatible = "ucc_geth";
-			model = "UCC";
 			cell-index = <4>;
-			device-id = <4>;
 			reg = <0x3200 0x200>;
 			interrupts = <35>;
 			interrupt-parent = <&qeic>;
@@ -287,8 +283,7 @@
 		ucc@2400 {
 			device_type = "serial";
 			compatible = "ucc_uart";
-			model = "UCC";
-			device-id = <5>;	/* The UCC number, 1-7*/
+			cell-index = <5>;	/* The UCC number, 1-7*/
 			port-number = <0>;	/* Which ttyQEx device */
 			soft-uart;		/* We need Soft-UART */
 			reg = <0x2400 0x200>;

arch/powerpc/boot/dts/mpc832x_rdb.dts

@@ -208,9 +208,7 @@
 		enet0: ucc@3000 {
 			device_type = "network";
 			compatible = "ucc_geth";
-			model = "UCC";
 			cell-index = <2>;
-			device-id = <2>;
 			reg = <0x3000 0x200>;
 			interrupts = <33>;
 			interrupt-parent = <&qeic>;
@@ -224,9 +222,7 @@
 		enet1: ucc@2200 {
 			device_type = "network";
 			compatible = "ucc_geth";
-			model = "UCC";
 			cell-index = <3>;
-			device-id = <3>;
 			reg = <0x2200 0x200>;
 			interrupts = <34>;
 			interrupt-parent = <&qeic>;

arch/powerpc/boot/dts/mpc836x_mds.dts

@@ -257,9 +257,7 @@
 		enet0: ucc@2000 {
 			device_type = "network";
 			compatible = "ucc_geth";
-			model = "UCC";
 			cell-index = <1>;
-			device-id = <1>;
 			reg = <0x2000 0x200>;
 			interrupts = <32>;
 			interrupt-parent = <&qeic>;
@@ -274,9 +272,7 @@
 		enet1: ucc@3000 {
 			device_type = "network";
 			compatible = "ucc_geth";
-			model = "UCC";
 			cell-index = <2>;
-			device-id = <2>;
 			reg = <0x3000 0x200>;
 			interrupts = <33>;
 			interrupt-parent = <&qeic>;

arch/powerpc/boot/dts/mpc8540ads.dts

@@ -1,7 +1,7 @@
 /*
  * MPC8540 ADS Device Tree Source
  *
- * Copyright 2006 Freescale Semiconductor Inc.
+ * Copyright 2006, 2008 Freescale Semiconductor Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -9,6 +9,7 @@
  * option) any later version.
  */
 
+/dts-v1/;
 
 / {
 	model = "MPC8540ADS";
@@ -31,11 +32,11 @@
 
 		PowerPC,8540@0 {
 			device_type = "cpu";
-			reg = <0>;
-			d-cache-line-size = <20>;	// 32 bytes
-			i-cache-line-size = <20>;	// 32 bytes
-			d-cache-size = <8000>;		// L1, 32K
-			i-cache-size = <8000>;		// L1, 32K
+			reg = <0x0>;
+			d-cache-line-size = <32>;	// 32 bytes
+			i-cache-line-size = <32>;	// 32 bytes
+			d-cache-size = <0x8000>;		// L1, 32K
+			i-cache-size = <0x8000>;		// L1, 32K
 			timebase-frequency = <0>;	//  33 MHz, from uboot
 			bus-frequency = <0>;	// 166 MHz
 			clock-frequency = <0>;	// 825 MHz, from uboot
@@ -44,31 +45,31 @@
 
 	memory {
 		device_type = "memory";
-		reg = <00000000 08000000>;	// 128M at 0x0
+		reg = <0x0 0x8000000>;	// 128M at 0x0
 	};
 
 	soc8540@e0000000 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		device_type = "soc";
-		ranges = <0 e0000000 00100000>;
-		reg = <e0000000 00100000>;	// CCSRBAR 1M
+		ranges = <0x0 0xe0000000 0x100000>;
+		reg = <0xe0000000 0x100000>;	// CCSRBAR 1M
 		bus-frequency = <0>;
 
 		memory-controller@2000 {
 			compatible = "fsl,8540-memory-controller";
-			reg = <2000 1000>;
+			reg = <0x2000 0x1000>;
 			interrupt-parent = <&mpic>;
-			interrupts = <12 2>;
+			interrupts = <18 2>;
 		};
 
 		l2-cache-controller@20000 {
 			compatible = "fsl,8540-l2-cache-controller";
-			reg = <20000 1000>;
-			cache-line-size = <20>;	// 32 bytes
-			cache-size = <40000>;	// L2, 256K
+			reg = <0x20000 0x1000>;
+			cache-line-size = <32>;	// 32 bytes
+			cache-size = <0x40000>;	// L2, 256K
 			interrupt-parent = <&mpic>;
-			interrupts = <10 2>;
+			interrupts = <16 2>;
 		};
 
 		i2c@3000 {
@@ -76,8 +77,8 @@
 			#size-cells = <0>;
 			cell-index = <0>;
 			compatible = "fsl-i2c";
-			reg = <3000 100>;
-			interrupts = <2b 2>;
+			reg = <0x3000 0x100>;
+			interrupts = <43 2>;
 			interrupt-parent = <&mpic>;
 			dfsrr;
 		};
@@ -86,24 +87,24 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			compatible = "fsl,gianfar-mdio";
-			reg = <24520 20>;
+			reg = <0x24520 0x20>;
 
 			phy0: ethernet-phy@0 {
 				interrupt-parent = <&mpic>;
 				interrupts = <5 1>;
-				reg = <0>;
+				reg = <0x0>;
 				device_type = "ethernet-phy";
 			};
 			phy1: ethernet-phy@1 {
 				interrupt-parent = <&mpic>;
 				interrupts = <5 1>;
-				reg = <1>;
+				reg = <0x1>;
 				device_type = "ethernet-phy";
 			};
 			phy3: ethernet-phy@3 {
 				interrupt-parent = <&mpic>;
 				interrupts = <7 1>;
-				reg = <3>;
+				reg = <0x3>;
 				device_type = "ethernet-phy";
 			};
 		};
@@ -113,9 +114,9 @@
 			device_type = "network";
 			model = "TSEC";
 			compatible = "gianfar";
-			reg = <24000 1000>;
+			reg = <0x24000 0x1000>;
 			local-mac-address = [ 00 00 00 00 00 00 ];
-			interrupts = <1d 2 1e 2 22 2>;
+			interrupts = <29 2 30 2 34 2>;
 			interrupt-parent = <&mpic>;
 			phy-handle = <&phy0>;
 		};
@@ -125,9 +126,9 @@
 			device_type = "network";
 			model = "TSEC";
 			compatible = "gianfar";
-			reg = <25000 1000>;
+			reg = <0x25000 0x1000>;
 			local-mac-address = [ 00 00 00 00 00 00 ];
-			interrupts = <23 2 24 2 28 2>;
+			interrupts = <35 2 36 2 40 2>;
 			interrupt-parent = <&mpic>;
 			phy-handle = <&phy1>;
 		};
@@ -137,9 +138,9 @@
 			device_type = "network";
 			model = "FEC";
 			compatible = "gianfar";
-			reg = <26000 1000>;
+			reg = <0x26000 0x1000>;
 			local-mac-address = [ 00 00 00 00 00 00 ];
-			interrupts = <29 2>;
+			interrupts = <41 2>;
 			interrupt-parent = <&mpic>;
 			phy-handle = <&phy3>;
 		};
@@ -148,9 +149,9 @@
 			cell-index = <0>;
 			device_type = "serial";
 			compatible = "ns16550";
-			reg = <4500 100>; 	// reg base, size
+			reg = <0x4500 0x100>; 	// reg base, size
 			clock-frequency = <0>; 	// should we fill in in uboot?
-			interrupts = <2a 2>;
+			interrupts = <42 2>;
 			interrupt-parent = <&mpic>;
 		};
 
@@ -158,9 +159,9 @@
 			cell-index = <1>;
 			device_type = "serial";
 			compatible = "ns16550";
-			reg = <4600 100>;	// reg base, size
+			reg = <0x4600 0x100>;	// reg base, size
 			clock-frequency = <0>; 	// should we fill in in uboot?
-			interrupts = <2a 2>;
+			interrupts = <42 2>;
 			interrupt-parent = <&mpic>;
 		};
 		mpic: pic@40000 {
@@ -168,7 +169,7 @@
 			interrupt-controller;
 			#address-cells = <0>;
 			#interrupt-cells = <2>;
-			reg = <40000 40000>;
+			reg = <0x40000 0x40000>;
 			compatible = "chrp,open-pic";
 			device_type = "open-pic";
 			big-endian;
@@ -177,90 +178,90 @@
 
 	pci0: pci@e0008000 {
 		cell-index = <0>;
-		interrupt-map-mask = <f800 0 0 7>;
+		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 		interrupt-map = <
 
 			/* IDSEL 0x02 */
-			1000 0 0 1 &mpic 1 1
-			1000 0 0 2 &mpic 2 1
-			1000 0 0 3 &mpic 3 1
-			1000 0 0 4 &mpic 4 1
+			0x1000 0x0 0x0 0x1 &mpic 0x1 0x1
+			0x1000 0x0 0x0 0x2 &mpic 0x2 0x1
+			0x1000 0x0 0x0 0x3 &mpic 0x3 0x1
+			0x1000 0x0 0x0 0x4 &mpic 0x4 0x1
 
 			/* IDSEL 0x03 */
-			1800 0 0 1 &mpic 4 1
-			1800 0 0 2 &mpic 1 1
-			1800 0 0 3 &mpic 2 1
-			1800 0 0 4 &mpic 3 1
+			0x1800 0x0 0x0 0x1 &mpic 0x4 0x1
+			0x1800 0x0 0x0 0x2 &mpic 0x1 0x1
+			0x1800 0x0 0x0 0x3 &mpic 0x2 0x1
+			0x1800 0x0 0x0 0x4 &mpic 0x3 0x1
 
 			/* IDSEL 0x04 */
-			2000 0 0 1 &mpic 3 1
-			2000 0 0 2 &mpic 4 1
-			2000 0 0 3 &mpic 1 1
-			2000 0 0 4 &mpic 2 1
+			0x2000 0x0 0x0 0x1 &mpic 0x3 0x1
+			0x2000 0x0 0x0 0x2 &mpic 0x4 0x1
+			0x2000 0x0 0x0 0x3 &mpic 0x1 0x1
+			0x2000 0x0 0x0 0x4 &mpic 0x2 0x1
 
 			/* IDSEL 0x05 */
-			2800 0 0 1 &mpic 2 1
-			2800 0 0 2 &mpic 3 1
-			2800 0 0 3 &mpic 4 1
-			2800 0 0 4 &mpic 1 1
+			0x2800 0x0 0x0 0x1 &mpic 0x2 0x1
+			0x2800 0x0 0x0 0x2 &mpic 0x3 0x1
+			0x2800 0x0 0x0 0x3 &mpic 0x4 0x1
+			0x2800 0x0 0x0 0x4 &mpic 0x1 0x1
 
 			/* IDSEL 0x0c */
-			6000 0 0 1 &mpic 1 1
-			6000 0 0 2 &mpic 2 1
-			6000 0 0 3 &mpic 3 1
-			6000 0 0 4 &mpic 4 1
+			0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
+			0x6000 0x0 0x0 0x2 &mpic 0x2 0x1
+			0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
+			0x6000 0x0 0x0 0x4 &mpic 0x4 0x1
 
 			/* IDSEL 0x0d */
-			6800 0 0 1 &mpic 4 1
-			6800 0 0 2 &mpic 1 1
-			6800 0 0 3 &mpic 2 1
-			6800 0 0 4 &mpic 3 1
+			0x6800 0x0 0x0 0x1 &mpic 0x4 0x1
+			0x6800 0x0 0x0 0x2 &mpic 0x1 0x1
+			0x6800 0x0 0x0 0x3 &mpic 0x2 0x1
+			0x6800 0x0 0x0 0x4 &mpic 0x3 0x1
 
 			/* IDSEL 0x0e */
-			7000 0 0 1 &mpic 3 1
-			7000 0 0 2 &mpic 4 1
-			7000 0 0 3 &mpic 1 1
-			7000 0 0 4 &mpic 2 1
+			0x7000 0x0 0x0 0x1 &mpic 0x3 0x1
+			0x7000 0x0 0x0 0x2 &mpic 0x4 0x1
+			0x7000 0x0 0x0 0x3 &mpic 0x1 0x1
+			0x7000 0x0 0x0 0x4 &mpic 0x2 0x1
 
 			/* IDSEL 0x0f */
-			7800 0 0 1 &mpic 2 1
-			7800 0 0 2 &mpic 3 1
-			7800 0 0 3 &mpic 4 1
-			7800 0 0 4 &mpic 1 1
+			0x7800 0x0 0x0 0x1 &mpic 0x2 0x1
+			0x7800 0x0 0x0 0x2 &mpic 0x3 0x1
+			0x7800 0x0 0x0 0x3 &mpic 0x4 0x1
+			0x7800 0x0 0x0 0x4 &mpic 0x1 0x1
 
 			/* IDSEL 0x12 */
-			9000 0 0 1 &mpic 1 1
-			9000 0 0 2 &mpic 2 1
-			9000 0 0 3 &mpic 3 1
-			9000 0 0 4 &mpic 4 1
+			0x9000 0x0 0x0 0x1 &mpic 0x1 0x1
+			0x9000 0x0 0x0 0x2 &mpic 0x2 0x1
+			0x9000 0x0 0x0 0x3 &mpic 0x3 0x1
+			0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
 
 			/* IDSEL 0x13 */
-			9800 0 0 1 &mpic 4 1
-			9800 0 0 2 &mpic 1 1
-			9800 0 0 3 &mpic 2 1
-			9800 0 0 4 &mpic 3 1
+			0x9800 0x0 0x0 0x1 &mpic 0x4 0x1
+			0x9800 0x0 0x0 0x2 &mpic 0x1 0x1
+			0x9800 0x0 0x0 0x3 &mpic 0x2 0x1
+			0x9800 0x0 0x0 0x4 &mpic 0x3 0x1
 
 			/* IDSEL 0x14 */
-			a000 0 0 1 &mpic 3 1
-			a000 0 0 2 &mpic 4 1
-			a000 0 0 3 &mpic 1 1
-			a000 0 0 4 &mpic 2 1
+			0xa000 0x0 0x0 0x1 &mpic 0x3 0x1
+			0xa000 0x0 0x0 0x2 &mpic 0x4 0x1
+			0xa000 0x0 0x0 0x3 &mpic 0x1 0x1
+			0xa000 0x0 0x0 0x4 &mpic 0x2 0x1
 
 			/* IDSEL 0x15 */
-			a800 0 0 1 &mpic 2 1
-			a800 0 0 2 &mpic 3 1
-			a800 0 0 3 &mpic 4 1
-			a800 0 0 4 &mpic 1 1>;
+			0xa800 0x0 0x0 0x1 &mpic 0x2 0x1
+			0xa800 0x0 0x0 0x2 &mpic 0x3 0x1
+			0xa800 0x0 0x0 0x3 &mpic 0x4 0x1
+			0xa800 0x0 0x0 0x4 &mpic 0x1 0x1>;
 		interrupt-parent = <&mpic>;
-		interrupts = <18 2>;
+		interrupts = <24 2>;
 		bus-range = <0 0>;
-		ranges = <02000000 0 80000000 80000000 0 20000000
-			  01000000 0 00000000 e2000000 0 00100000>;
-		clock-frequency = <3f940aa>;
+		ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
+			  0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
+		clock-frequency = <66666666>;
 		#interrupt-cells = <1>;
 		#size-cells = <2>;
 		#address-cells = <3>;
-		reg = <e0008000 1000>;
+		reg = <0xe0008000 0x1000>;
 		compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
 		device_type = "pci";
 	};

arch/powerpc/boot/dts/mpc8541cds.dts

@@ -1,7 +1,7 @@
 /*
  * MPC8541 CDS Device Tree Source
  *
- * Copyright 2006 Freescale Semiconductor Inc.
+ * Copyright 2006, 2008 Freescale Semiconductor Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -9,6 +9,7 @@
  * option) any later version.
  */
 
+/dts-v1/;
 
 / {
 	model = "MPC8541CDS";
@@ -31,11 +32,11 @@
 
 		PowerPC,8541@0 {
 			device_type = "cpu";
-			reg = <0>;
-			d-cache-line-size = <20>;	// 32 bytes
-			i-cache-line-size = <20>;	// 32 bytes
-			d-cache-size = <8000>;		// L1, 32K
-			i-cache-size = <8000>;		// L1, 32K
+			reg = <0x0>;
+			d-cache-line-size = <32>;	// 32 bytes
+			i-cache-line-size = <32>;	// 32 bytes
+			d-cache-size = <0x8000>;		// L1, 32K
+			i-cache-size = <0x8000>;		// L1, 32K
 			timebase-frequency = <0>;	//  33 MHz, from uboot
 			bus-frequency = <0>;	// 166 MHz
 			clock-frequency = <0>;	// 825 MHz, from uboot
@@ -44,31 +45,31 @@
 
 	memory {
 		device_type = "memory";
-		reg = <00000000 08000000>;	// 128M at 0x0
+		reg = <0x0 0x8000000>;	// 128M at 0x0
 	};
 
 	soc8541@e0000000 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		device_type = "soc";
-		ranges = <0 e0000000 00100000>;
-		reg = <e0000000 00001000>;	// CCSRBAR 1M
+		ranges = <0x0 0xe0000000 0x100000>;
+		reg = <0xe0000000 0x1000>;	// CCSRBAR 1M
 		bus-frequency = <0>;
 
 		memory-controller@2000 {
 			compatible = "fsl,8541-memory-controller";
-			reg = <2000 1000>;
+			reg = <0x2000 0x1000>;
 			interrupt-parent = <&mpic>;
-			interrupts = <12 2>;
+			interrupts = <18 2>;
 		};
 
 		l2-cache-controller@20000 {
 			compatible = "fsl,8541-l2-cache-controller";
-			reg = <20000 1000>;
-			cache-line-size = <20>;	// 32 bytes
-			cache-size = <40000>;	// L2, 256K
+			reg = <0x20000 0x1000>;
+			cache-line-size = <32>;	// 32 bytes
+			cache-size = <0x40000>;	// L2, 256K
 			interrupt-parent = <&mpic>;
-			interrupts = <10 2>;
+			interrupts = <16 2>;
 		};
 
 		i2c@3000 {
@@ -76,8 +77,8 @@
 			#size-cells = <0>;
 			cell-index = <0>;
 			compatible = "fsl-i2c";
-			reg = <3000 100>;
-			interrupts = <2b 2>;
+			reg = <0x3000 0x100>;
+			interrupts = <43 2>;
 			interrupt-parent = <&mpic>;
 			dfsrr;
 		};
@@ -86,18 +87,18 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			compatible = "fsl,gianfar-mdio";
-			reg = <24520 20>;
+			reg = <0x24520 0x20>;
 
 			phy0: ethernet-phy@0 {
 				interrupt-parent = <&mpic>;
 				interrupts = <5 1>;
-				reg = <0>;
+				reg = <0x0>;
 				device_type = "ethernet-phy";
 			};
 			phy1: ethernet-phy@1 {
 				interrupt-parent = <&mpic>;
 				interrupts = <5 1>;
-				reg = <1>;
+				reg = <0x1>;
 				device_type = "ethernet-phy";
 			};
 		};
@@ -107,9 +108,9 @@
 			device_type = "network";
 			model = "TSEC";
 			compatible = "gianfar";
-			reg = <24000 1000>;
+			reg = <0x24000 0x1000>;
 			local-mac-address = [ 00 00 00 00 00 00 ];
-			interrupts = <1d 2 1e 2 22 2>;
+			interrupts = <29 2 30 2 34 2>;
 			interrupt-parent = <&mpic>;
 			phy-handle = <&phy0>;
 		};
@@ -119,9 +120,9 @@
 			device_type = "network";
 			model = "TSEC";
 			compatible = "gianfar";
-			reg = <25000 1000>;
+			reg = <0x25000 0x1000>;
 			local-mac-address = [ 00 00 00 00 00 00 ];
-			interrupts = <23 2 24 2 28 2>;
+			interrupts = <35 2 36 2 40 2>;
 			interrupt-parent = <&mpic>;
 			phy-handle = <&phy1>;
 		};
@@ -130,9 +131,9 @@
 			cell-index = <0>;
 			device_type = "serial";
 			compatible = "ns16550";
-			reg = <4500 100>; 	// reg base, size
+			reg = <0x4500 0x100>; 	// reg base, size
 			clock-frequency = <0>; 	// should we fill in in uboot?
-			interrupts = <2a 2>;
+			interrupts = <42 2>;
 			interrupt-parent = <&mpic>;
 		};
 
@@ -140,9 +141,9 @@
 			cell-index = <1>;
 			device_type = "serial";
 			compatible = "ns16550";
-			reg = <4600 100>;	// reg base, size
+			reg = <0x4600 0x100>;	// reg base, size
 			clock-frequency = <0>; 	// should we fill in in uboot?
-			interrupts = <2a 2>;
+			interrupts = <42 2>;
 			interrupt-parent = <&mpic>;
 		};
 
@@ -151,7 +152,7 @@
 			interrupt-controller;
 			#address-cells = <0>;
 			#interrupt-cells = <2>;
-			reg = <40000 40000>;
+			reg = <0x40000 0x40000>;
 			compatible = "chrp,open-pic";
 			device_type = "open-pic";
                         big-endian;
@@ -161,17 +162,17 @@
 			#address-cells = <1>;
 			#size-cells = <1>;
 			compatible = "fsl,mpc8541-cpm", "fsl,cpm2";
-			reg = <919c0 30>;
+			reg = <0x919c0 0x30>;
 			ranges;
 
 			muram@80000 {
 				#address-cells = <1>;
 				#size-cells = <1>;
-				ranges = <0 80000 10000>;
+				ranges = <0x0 0x80000 0x10000>;
 
 				data@0 {
 					compatible = "fsl,cpm-muram-data";
-					reg = <0 2000 9000 1000>;
+					reg = <0x0 0x2000 0x9000 0x1000>;
 				};
 			};
 
@@ -179,16 +180,16 @@
 				compatible = "fsl,mpc8541-brg",
 				             "fsl,cpm2-brg",
 				             "fsl,cpm-brg";
-				reg = <919f0 10 915f0 10>;
+				reg = <0x919f0 0x10 0x915f0 0x10>;
 			};
 
 			cpmpic: pic@90c00 {
 				interrupt-controller;
 				#address-cells = <0>;
 				#interrupt-cells = <2>;
-				interrupts = <2e 2>;
+				interrupts = <46 2>;
 				interrupt-parent = <&mpic>;
-				reg = <90c00 80>;
+				reg = <0x90c00 0x80>;
 				compatible = "fsl,mpc8541-cpm-pic", "fsl,cpm2-pic";
 			};
 		};
@@ -196,68 +197,68 @@
 
 	pci0: pci@e0008000 {
 		cell-index = <0>;
-		interrupt-map-mask = <1f800 0 0 7>;
+		interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
 		interrupt-map = <
 
 			/* IDSEL 0x10 */
-			08000 0 0 1 &mpic 0 1
-			08000 0 0 2 &mpic 1 1
-			08000 0 0 3 &mpic 2 1
-			08000 0 0 4 &mpic 3 1
+			0x8000 0x0 0x0 0x1 &mpic 0x0 0x1
+			0x8000 0x0 0x0 0x2 &mpic 0x1 0x1
+			0x8000 0x0 0x0 0x3 &mpic 0x2 0x1
+			0x8000 0x0 0x0 0x4 &mpic 0x3 0x1
 
 			/* IDSEL 0x11 */
-			08800 0 0 1 &mpic 0 1
-			08800 0 0 2 &mpic 1 1
-			08800 0 0 3 &mpic 2 1
-			08800 0 0 4 &mpic 3 1
+			0x8800 0x0 0x0 0x1 &mpic 0x0 0x1
+			0x8800 0x0 0x0 0x2 &mpic 0x1 0x1
+			0x8800 0x0 0x0 0x3 &mpic 0x2 0x1
+			0x8800 0x0 0x0 0x4 &mpic 0x3 0x1
 
 			/* IDSEL 0x12 (Slot 1) */
-			09000 0 0 1 &mpic 0 1
-			09000 0 0 2 &mpic 1 1
-			09000 0 0 3 &mpic 2 1
-			09000 0 0 4 &mpic 3 1
+			0x9000 0x0 0x0 0x1 &mpic 0x0 0x1
+			0x9000 0x0 0x0 0x2 &mpic 0x1 0x1
+			0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
+			0x9000 0x0 0x0 0x4 &mpic 0x3 0x1
 
 			/* IDSEL 0x13 (Slot 2) */
-			09800 0 0 1 &mpic 1 1
-			09800 0 0 2 &mpic 2 1
-			09800 0 0 3 &mpic 3 1
-			09800 0 0 4 &mpic 0 1
+			0x9800 0x0 0x0 0x1 &mpic 0x1 0x1
+			0x9800 0x0 0x0 0x2 &mpic 0x2 0x1
+			0x9800 0x0 0x0 0x3 &mpic 0x3 0x1
+			0x9800 0x0 0x0 0x4 &mpic 0x0 0x1
 
 			/* IDSEL 0x14 (Slot 3) */
-			0a000 0 0 1 &mpic 2 1
-			0a000 0 0 2 &mpic 3 1
-			0a000 0 0 3 &mpic 0 1
-			0a000 0 0 4 &mpic 1 1
+			0xa000 0x0 0x0 0x1 &mpic 0x2 0x1
+			0xa000 0x0 0x0 0x2 &mpic 0x3 0x1
+			0xa000 0x0 0x0 0x3 &mpic 0x0 0x1
+			0xa000 0x0 0x0 0x4 &mpic 0x1 0x1
 
 			/* IDSEL 0x15 (Slot 4) */
-			0a800 0 0 1 &mpic 3 1
-			0a800 0 0 2 &mpic 0 1
-			0a800 0 0 3 &mpic 1 1
-			0a800 0 0 4 &mpic 2 1
+			0xa800 0x0 0x0 0x1 &mpic 0x3 0x1
+			0xa800 0x0 0x0 0x2 &mpic 0x0 0x1
+			0xa800 0x0 0x0 0x3 &mpic 0x1 0x1
+			0xa800 0x0 0x0 0x4 &mpic 0x2 0x1
 
 			/* Bus 1 (Tundra Bridge) */
 			/* IDSEL 0x12 (ISA bridge) */
-			19000 0 0 1 &mpic 0 1
-			19000 0 0 2 &mpic 1 1
-			19000 0 0 3 &mpic 2 1
-			19000 0 0 4 &mpic 3 1>;
+			0x19000 0x0 0x0 0x1 &mpic 0x0 0x1
+			0x19000 0x0 0x0 0x2 &mpic 0x1 0x1
+			0x19000 0x0 0x0 0x3 &mpic 0x2 0x1
+			0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>;
 		interrupt-parent = <&mpic>;
-		interrupts = <18 2>;
+		interrupts = <24 2>;
 		bus-range = <0 0>;
-		ranges = <02000000 0 80000000 80000000 0 20000000
-			  01000000 0 00000000 e2000000 0 00100000>;
-		clock-frequency = <3f940aa>;
+		ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
+			  0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
+		clock-frequency = <66666666>;
 		#interrupt-cells = <1>;
 		#size-cells = <2>;
 		#address-cells = <3>;
-		reg = <e0008000 1000>;
+		reg = <0xe0008000 0x1000>;
 		compatible = "fsl,mpc8540-pci";
 		device_type = "pci";
 
 		i8259@19000 {
 			interrupt-controller;
 			device_type = "interrupt-controller";
-			reg = <19000 0 0 0 1>;
+			reg = <0x19000 0x0 0x0 0x0 0x1>;
 			#address-cells = <0>;
 			#interrupt-cells = <2>;
 			compatible = "chrp,iic";
@@ -268,24 +269,24 @@
 
 	pci1: pci@e0009000 {
 		cell-index = <1>;
-		interrupt-map-mask = <f800 0 0 7>;
+		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 		interrupt-map = <
 
 			/* IDSEL 0x15 */
-			a800 0 0 1 &mpic b 1
-			a800 0 0 2 &mpic b 1
-			a800 0 0 3 &mpic b 1
-			a800 0 0 4 &mpic b 1>;
+			0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
+			0xa800 0x0 0x0 0x2 &mpic 0xb 0x1
+			0xa800 0x0 0x0 0x3 &mpic 0xb 0x1
+			0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>;
 		interrupt-parent = <&mpic>;
-		interrupts = <19 2>;
+		interrupts = <25 2>;
 		bus-range = <0 0>;
-		ranges = <02000000 0 a0000000 a0000000 0 20000000
-			  01000000 0 00000000 e3000000 0 00100000>;
-		clock-frequency = <3f940aa>;
+		ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
+			  0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
+		clock-frequency = <66666666>;
 		#interrupt-cells = <1>;
 		#size-cells = <2>;
 		#address-cells = <3>;
-		reg = <e0009000 1000>;
+		reg = <0xe0009000 0x1000>;
 		compatible = "fsl,mpc8540-pci";
 		device_type = "pci";
 	};

arch/powerpc/boot/dts/mpc8544ds.dts

@@ -1,7 +1,7 @@
 /*
  * MPC8544 DS Device Tree Source
  *
- * Copyright 2007 Freescale Semiconductor Inc.
+ * Copyright 2007, 2008 Freescale Semiconductor Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -9,6 +9,7 @@
  * option) any later version.
  */
 
+/dts-v1/;
 / {
 	model = "MPC8544DS";
 	compatible = "MPC8544DS", "MPC85xxDS";
@@ -27,17 +28,16 @@
 	};
 
 	cpus {
-		#cpus = <1>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 
 		PowerPC,8544@0 {
 			device_type = "cpu";
-			reg = <0>;
-			d-cache-line-size = <20>;	// 32 bytes
-			i-cache-line-size = <20>;	// 32 bytes
-			d-cache-size = <8000>;		// L1, 32K
-			i-cache-size = <8000>;		// L1, 32K
+			reg = <0x0>;
+			d-cache-line-size = <32>;	// 32 bytes
+			i-cache-line-size = <32>;	// 32 bytes
+			d-cache-size = <0x8000>;		// L1, 32K
+			i-cache-size = <0x8000>;		// L1, 32K
 			timebase-frequency = <0>;
 			bus-frequency = <0>;
 			clock-frequency = <0>;
@@ -46,7 +46,7 @@
 
 	memory {
 		device_type = "memory";
-		reg = <00000000 00000000>;	// Filled by U-Boot
+		reg = <0x0 0x0>;	// Filled by U-Boot
 	};
 
 	soc8544@e0000000 {
@@ -54,24 +54,24 @@
 		#size-cells = <1>;
 		device_type = "soc";
 
-		ranges = <00000000 e0000000 00100000>;
-		reg = <e0000000 00001000>;	// CCSRBAR 1M
+		ranges = <0x0 0xe0000000 0x100000>;
+		reg = <0xe0000000 0x1000>;	// CCSRBAR 1M
 		bus-frequency = <0>;		// Filled out by uboot.
 
 		memory-controller@2000 {
 			compatible = "fsl,8544-memory-controller";
-			reg = <2000 1000>;
+			reg = <0x2000 0x1000>;
 			interrupt-parent = <&mpic>;
-			interrupts = <12 2>;
+			interrupts = <18 2>;
 		};
 
 		l2-cache-controller@20000 {
 			compatible = "fsl,8544-l2-cache-controller";
-			reg = <20000 1000>;
-			cache-line-size = <20>;	// 32 bytes
-			cache-size = <40000>;	// L2, 256K
+			reg = <0x20000 0x1000>;
+			cache-line-size = <32>;	// 32 bytes
+			cache-size = <0x40000>;	// L2, 256K
 			interrupt-parent = <&mpic>;
-			interrupts = <10 2>;
+			interrupts = <16 2>;
 		};
 
 		i2c@3000 {
@@ -79,8 +79,8 @@
 			#size-cells = <0>;
 			cell-index = <0>;
 			compatible = "fsl-i2c";
-			reg = <3000 100>;
-			interrupts = <2b 2>;
+			reg = <0x3000 0x100>;
+			interrupts = <43 2>;
 			interrupt-parent = <&mpic>;
 			dfsrr;
 		};
@@ -90,8 +90,8 @@
 			#size-cells = <0>;
 			cell-index = <1>;
 			compatible = "fsl-i2c";
-			reg = <3100 100>;
-			interrupts = <2b 2>;
+			reg = <0x3100 0x100>;
+			interrupts = <43 2>;
 			interrupt-parent = <&mpic>;
 			dfsrr;
 		};
@@ -100,30 +100,71 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			compatible = "fsl,gianfar-mdio";
-			reg = <24520 20>;
+			reg = <0x24520 0x20>;
 
 			phy0: ethernet-phy@0 {
 				interrupt-parent = <&mpic>;
-				interrupts = <a 1>;
-				reg = <0>;
+				interrupts = <10 1>;
+				reg = <0x0>;
 				device_type = "ethernet-phy";
 			};
 			phy1: ethernet-phy@1 {
 				interrupt-parent = <&mpic>;
-				interrupts = <a 1>;
-				reg = <1>;
+				interrupts = <10 1>;
+				reg = <0x1>;
 				device_type = "ethernet-phy";
 			};
 		};
 
+		dma@21300 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "fsl,mpc8544-dma", "fsl,eloplus-dma";
+			reg = <0x21300 0x4>;
+			ranges = <0x0 0x21100 0x200>;
+			cell-index = <0>;
+			dma-channel@0 {
+				compatible = "fsl,mpc8544-dma-channel",
+						"fsl,eloplus-dma-channel";
+				reg = <0x0 0x80>;
+				cell-index = <0>;
+				interrupt-parent = <&mpic>;
+				interrupts = <20 2>;
+			};
+			dma-channel@80 {
+				compatible = "fsl,mpc8544-dma-channel",
+						"fsl,eloplus-dma-channel";
+				reg = <0x80 0x80>;
+				cell-index = <1>;
+				interrupt-parent = <&mpic>;
+				interrupts = <21 2>;
+			};
+			dma-channel@100 {
+				compatible = "fsl,mpc8544-dma-channel",
+						"fsl,eloplus-dma-channel";
+				reg = <0x100 0x80>;
+				cell-index = <2>;
+				interrupt-parent = <&mpic>;
+				interrupts = <22 2>;
+			};
+			dma-channel@180 {
+				compatible = "fsl,mpc8544-dma-channel",
+						"fsl,eloplus-dma-channel";
+				reg = <0x180 0x80>;
+				cell-index = <3>;
+				interrupt-parent = <&mpic>;
+				interrupts = <23 2>;
+			};
+		};
+
 		enet0: ethernet@24000 {
 			cell-index = <0>;
 			device_type = "network";
 			model = "TSEC";
 			compatible = "gianfar";
-			reg = <24000 1000>;
+			reg = <0x24000 0x1000>;
 			local-mac-address = [ 00 00 00 00 00 00 ];
-			interrupts = <1d 2 1e 2 22 2>;
+			interrupts = <29 2 30 2 34 2>;
 			interrupt-parent = <&mpic>;
 			phy-handle = <&phy0>;
 			phy-connection-type = "rgmii-id";
@@ -134,9 +175,9 @@
 			device_type = "network";
 			model = "TSEC";
 			compatible = "gianfar";
-			reg = <26000 1000>;
+			reg = <0x26000 0x1000>;
 			local-mac-address = [ 00 00 00 00 00 00 ];
-			interrupts = <1f 2 20 2 21 2>;
+			interrupts = <31 2 32 2 33 2>;
 			interrupt-parent = <&mpic>;
 			phy-handle = <&phy1>;
 			phy-connection-type = "rgmii-id";
@@ -146,9 +187,9 @@
 			cell-index = <0>;
 			device_type = "serial";
 			compatible = "ns16550";
-			reg = <4500 100>;
+			reg = <0x4500 0x100>;
 			clock-frequency = <0>;
-			interrupts = <2a 2>;
+			interrupts = <42 2>;
 			interrupt-parent = <&mpic>;
 		};
 
@@ -156,15 +197,15 @@
 			cell-index = <1>;
 			device_type = "serial";
 			compatible = "ns16550";
-			reg = <4600 100>;
+			reg = <0x4600 0x100>;
 			clock-frequency = <0>;
-			interrupts = <2a 2>;
+			interrupts = <42 2>;
 			interrupt-parent = <&mpic>;
 		};
 
 		global-utilities@e0000 {	//global utilities block
 			compatible = "fsl,mpc8548-guts";
-			reg = <e0000 1000>;
+			reg = <0xe0000 0x1000>;
 			fsl,has-rstcr;
 		};
 
@@ -173,7 +214,7 @@
 			interrupt-controller;
 			#address-cells = <0>;
 			#interrupt-cells = <2>;
-			reg = <40000 40000>;
+			reg = <0x40000 0x40000>;
 			compatible = "chrp,open-pic";
 			device_type = "open-pic";
 			big-endian;
@@ -184,32 +225,32 @@
 		cell-index = <0>;
 		compatible = "fsl,mpc8540-pci";
 		device_type = "pci";
-		interrupt-map-mask = <f800 0 0 7>;
+		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 		interrupt-map = <
 
 			/* IDSEL 0x11 J17 Slot 1 */
-			8800 0 0 1 &mpic 2 1
-			8800 0 0 2 &mpic 3 1
-			8800 0 0 3 &mpic 4 1
-			8800 0 0 4 &mpic 1 1
+			0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
+			0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
+			0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
+			0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
 
 			/* IDSEL 0x12 J16 Slot 2 */
 
-			9000 0 0 1 &mpic 3 1
-			9000 0 0 2 &mpic 4 1
-			9000 0 0 3 &mpic 2 1
-			9000 0 0 4 &mpic 1 1>;
+			0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
+			0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
+			0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
+			0x9000 0x0 0x0 0x4 &mpic 0x1 0x1>;
 
 		interrupt-parent = <&mpic>;
-		interrupts = <18 2>;
-		bus-range = <0 ff>;
-		ranges = <02000000 0 c0000000 c0000000 0 20000000
-			  01000000 0 00000000 e1000000 0 00010000>;
-		clock-frequency = <3f940aa>;
+		interrupts = <24 2>;
+		bus-range = <0 255>;
+		ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
+			  0x1000000 0x0 0x0 0xe1000000 0x0 0x10000>;
+		clock-frequency = <66666666>;
 		#interrupt-cells = <1>;
 		#size-cells = <2>;
 		#address-cells = <3>;
-		reg = <e0008000 1000>;
+		reg = <0xe0008000 0x1000>;
 	};
 
 	pci1: pcie@e0009000 {
@@ -219,33 +260,33 @@
 		#interrupt-cells = <1>;
 		#size-cells = <2>;
 		#address-cells = <3>;
-		reg = <e0009000 1000>;
-		bus-range = <0 ff>;
-		ranges = <02000000 0 80000000 80000000 0 20000000
-			  01000000 0 00000000 e1010000 0 00010000>;
-		clock-frequency = <1fca055>;
+		reg = <0xe0009000 0x1000>;
+		bus-range = <0 255>;
+		ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
+			  0x1000000 0x0 0x0 0xe1010000 0x0 0x10000>;
+		clock-frequency = <33333333>;
 		interrupt-parent = <&mpic>;
-		interrupts = <1a 2>;
-		interrupt-map-mask = <f800 0 0 7>;
+		interrupts = <26 2>;
+		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 		interrupt-map = <
 			/* IDSEL 0x0 */
-			0000 0 0 1 &mpic 4 1
-			0000 0 0 2 &mpic 5 1
-			0000 0 0 3 &mpic 6 1
-			0000 0 0 4 &mpic 7 1
+			0000 0x0 0x0 0x1 &mpic 0x4 0x1
+			0000 0x0 0x0 0x2 &mpic 0x5 0x1
+			0000 0x0 0x0 0x3 &mpic 0x6 0x1
+			0000 0x0 0x0 0x4 &mpic 0x7 0x1
 			>;
 		pcie@0 {
-			reg = <0 0 0 0 0>;
+			reg = <0x0 0x0 0x0 0x0 0x0>;
 			#size-cells = <2>;
 			#address-cells = <3>;
 			device_type = "pci";
-			ranges = <02000000 0 80000000
-				  02000000 0 80000000
-				  0 20000000
+			ranges = <0x2000000 0x0 0x80000000
+				  0x2000000 0x0 0x80000000
+				  0x0 0x20000000
 
-				  01000000 0 00000000
-				  01000000 0 00000000
-				  0 00010000>;
+				  0x1000000 0x0 0x0
+				  0x1000000 0x0 0x0
+				  0x0 0x10000>;
 		};
 	};
 
@@ -256,33 +297,33 @@
 		#interrupt-cells = <1>;
 		#size-cells = <2>;
 		#address-cells = <3>;
-		reg = <e000a000 1000>;
-		bus-range = <0 ff>;
-		ranges = <02000000 0 a0000000 a0000000 0 10000000
-			  01000000 0 00000000 e1020000 0 00010000>;
-		clock-frequency = <1fca055>;
+		reg = <0xe000a000 0x1000>;
+		bus-range = <0 255>;
+		ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
+			  0x1000000 0x0 0x0 0xe1020000 0x0 0x10000>;
+		clock-frequency = <33333333>;
 		interrupt-parent = <&mpic>;
-		interrupts = <19 2>;
-		interrupt-map-mask = <f800 0 0 7>;
+		interrupts = <25 2>;
+		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 		interrupt-map = <
 			/* IDSEL 0x0 */
-			0000 0 0 1 &mpic 0 1
-			0000 0 0 2 &mpic 1 1
-			0000 0 0 3 &mpic 2 1
-			0000 0 0 4 &mpic 3 1
+			0000 0x0 0x0 0x1 &mpic 0x0 0x1
+			0000 0x0 0x0 0x2 &mpic 0x1 0x1
+			0000 0x0 0x0 0x3 &mpic 0x2 0x1
+			0000 0x0 0x0 0x4 &mpic 0x3 0x1
 			>;
 		pcie@0 {
-			reg = <0 0 0 0 0>;
+			reg = <0x0 0x0 0x0 0x0 0x0>;
 			#size-cells = <2>;
 			#address-cells = <3>;
 			device_type = "pci";
-			ranges = <02000000 0 a0000000
-				  02000000 0 a0000000
-				  0 10000000
+			ranges = <0x2000000 0x0 0xa0000000
+				  0x2000000 0x0 0xa0000000
+				  0x0 0x10000000
 
-				  01000000 0 00000000
-				  01000000 0 00000000
-				  0 00010000>;
+				  0x1000000 0x0 0x0
+				  0x1000000 0x0 0x0
+				  0x0 0x10000>;
 		};
 	};
 
@@ -293,72 +334,72 @@
 		#interrupt-cells = <1>;
 		#size-cells = <2>;
 		#address-cells = <3>;
-		reg = <e000b000 1000>;
-		bus-range = <0 ff>;
-		ranges = <02000000 0 b0000000 b0000000 0 00100000
-			  01000000 0 00000000 b0100000 0 00100000>;
-		clock-frequency = <1fca055>;
+		reg = <0xe000b000 0x1000>;
+		bus-range = <0 255>;
+		ranges = <0x2000000 0x0 0xb0000000 0xb0000000 0x0 0x100000
+			  0x1000000 0x0 0x0 0xb0100000 0x0 0x100000>;
+		clock-frequency = <33333333>;
 		interrupt-parent = <&mpic>;
-		interrupts = <1b 2>;
-		interrupt-map-mask = <ff00 0 0 1>;
+		interrupts = <27 2>;
+		interrupt-map-mask = <0xff00 0x0 0x0 0x1>;
 		interrupt-map = <
 			// IDSEL 0x1c  USB
-			e000 0 0 1 &i8259 c 2
-			e100 0 0 2 &i8259 9 2
-			e200 0 0 3 &i8259 a 2
-			e300 0 0 4 &i8259 b 2
+			0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
+			0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
+			0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
+			0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
 
 			// IDSEL 0x1d  Audio
-			e800 0 0 1 &i8259 6 2
+			0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
 
 			// IDSEL 0x1e Legacy
-			f000 0 0 1 &i8259 7 2
-			f100 0 0 1 &i8259 7 2
+			0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
+			0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
 
 			// IDSEL 0x1f IDE/SATA
-			f800 0 0 1 &i8259 e 2
-			f900 0 0 1 &i8259 5 2
+			0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
+			0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
 		>;
 
 		pcie@0 {
-			reg = <0 0 0 0 0>;
+			reg = <0x0 0x0 0x0 0x0 0x0>;
 			#size-cells = <2>;
 			#address-cells = <3>;
 			device_type = "pci";
-			ranges = <02000000 0 b0000000
-				  02000000 0 b0000000
-				  0 00100000
+			ranges = <0x2000000 0x0 0xb0000000
+				  0x2000000 0x0 0xb0000000
+				  0x0 0x100000
 
-				  01000000 0 00000000
-				  01000000 0 00000000
-				  0 00100000>;
+				  0x1000000 0x0 0x0
+				  0x1000000 0x0 0x0
+				  0x0 0x100000>;
 
 			uli1575@0 {
-				reg = <0 0 0 0 0>;
+				reg = <0x0 0x0 0x0 0x0 0x0>;
 				#size-cells = <2>;
 				#address-cells = <3>;
-				ranges = <02000000 0 b0000000
-					  02000000 0 b0000000
-					  0 00100000
+				ranges = <0x2000000 0x0 0xb0000000
+					  0x2000000 0x0 0xb0000000
+					  0x0 0x100000
 
-					  01000000 0 00000000
-					  01000000 0 00000000
-					  0 00100000>;
+					  0x1000000 0x0 0x0
+					  0x1000000 0x0 0x0
+					  0x0 0x100000>;
 				isa@1e {
 					device_type = "isa";
 					#interrupt-cells = <2>;
 					#size-cells = <1>;
 					#address-cells = <2>;
-					reg = <f000 0 0 0 0>;
-					ranges = <1 0
-						  01000000 0 0
-						  00001000>;
+					reg = <0xf000 0x0 0x0 0x0 0x0>;
+					ranges = <0x1 0x0
+						  0x1000000 0x0 0x0
+						  0x1000>;
 					interrupt-parent = <&i8259>;
 
 					i8259: interrupt-controller@20 {
-						reg = <1 20 2
-						       1 a0 2
-						       1 4d0 2>;
+						reg = <0x1 0x20 0x2
+						       0x1 0xa0 0x2
+						       0x1 0x4d0 0x2>;
 						interrupt-controller;
 						device_type = "interrupt-controller";
 						#address-cells = <0>;
@@ -371,28 +412,28 @@
 					i8042@60 {
 						#size-cells = <0>;
 						#address-cells = <1>;
-						reg = <1 60 1 1 64 1>;
-						interrupts = <1 3 c 3>;
+						reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
+						interrupts = <1 3 12 3>;
 						interrupt-parent = <&i8259>;
 
 						keyboard@0 {
-							reg = <0>;
+							reg = <0x0>;
 							compatible = "pnpPNP,303";
 						};
 
 						mouse@1 {
-							reg = <1>;
+							reg = <0x1>;
 							compatible = "pnpPNP,f03";
 						};
 					};
 
 					rtc@70 {
 						compatible = "pnpPNP,b00";
-						reg = <1 70 2>;
+						reg = <0x1 0x70 0x2>;
 					};
 
 					gpio@400 {
-						reg = <1 400 80>;
+						reg = <0x1 0x400 0x80>;
 					};
 				};
 			};

arch/powerpc/boot/dts/mpc8548cds.dts

@@ -1,7 +1,7 @@
 /*
  * MPC8548 CDS Device Tree Source
  *
- * Copyright 2006 Freescale Semiconductor Inc.
+ * Copyright 2006, 2008 Freescale Semiconductor Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -9,6 +9,7 @@
  * option) any later version.
  */
 
+/dts-v1/;
 
 / {
 	model = "MPC8548CDS";
@@ -36,11 +37,11 @@
 
 		PowerPC,8548@0 {
 			device_type = "cpu";
-			reg = <0>;
-			d-cache-line-size = <20>;	// 32 bytes
-			i-cache-line-size = <20>;	// 32 bytes
-			d-cache-size = <8000>;		// L1, 32K
-			i-cache-size = <8000>;		// L1, 32K
+			reg = <0x0>;
+			d-cache-line-size = <32>;	// 32 bytes
+			i-cache-line-size = <32>;	// 32 bytes
+			d-cache-size = <0x8000>;		// L1, 32K
+			i-cache-size = <0x8000>;		// L1, 32K
 			timebase-frequency = <0>;	//  33 MHz, from uboot
 			bus-frequency = <0>;	// 166 MHz
 			clock-frequency = <0>;	// 825 MHz, from uboot
@@ -49,31 +50,31 @@
 
 	memory {
 		device_type = "memory";
-		reg = <00000000 08000000>;	// 128M at 0x0
+		reg = <0x0 0x8000000>;	// 128M at 0x0
 	};
 
 	soc8548@e0000000 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		device_type = "soc";
-		ranges = <00000000 e0000000 00100000>;
-		reg = <e0000000 00001000>;	// CCSRBAR
+		ranges = <0x0 0xe0000000 0x100000>;
+		reg = <0xe0000000 0x1000>;	// CCSRBAR
 		bus-frequency = <0>;
 
 		memory-controller@2000 {
 			compatible = "fsl,8548-memory-controller";
-			reg = <2000 1000>;
+			reg = <0x2000 0x1000>;
 			interrupt-parent = <&mpic>;
-			interrupts = <12 2>;
+			interrupts = <18 2>;
 		};
 
 		l2-cache-controller@20000 {
 			compatible = "fsl,8548-l2-cache-controller";
-			reg = <20000 1000>;
-			cache-line-size = <20>;	// 32 bytes
-			cache-size = <80000>;	// L2, 512K
+			reg = <0x20000 0x1000>;
+			cache-line-size = <32>;	// 32 bytes
+			cache-size = <0x80000>;	// L2, 512K
 			interrupt-parent = <&mpic>;
-			interrupts = <10 2>;
+			interrupts = <16 2>;
 		};
 
 		i2c@3000 {
@@ -81,8 +82,8 @@
 			#size-cells = <0>;
 			cell-index = <0>;
 			compatible = "fsl-i2c";
-			reg = <3000 100>;
-			interrupts = <2b 2>;
+			reg = <0x3000 0x100>;
+			interrupts = <43 2>;
 			interrupt-parent = <&mpic>;
 			dfsrr;
 		};
@@ -92,8 +93,8 @@
 			#size-cells = <0>;
 			cell-index = <1>;
 			compatible = "fsl-i2c";
-			reg = <3100 100>;
-			interrupts = <2b 2>;
+			reg = <0x3100 0x100>;
+			interrupts = <43 2>;
 			interrupt-parent = <&mpic>;
 			dfsrr;
 		};
@@ -102,30 +103,30 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			compatible = "fsl,gianfar-mdio";
-			reg = <24520 20>;
+			reg = <0x24520 0x20>;
 
 			phy0: ethernet-phy@0 {
 				interrupt-parent = <&mpic>;
 				interrupts = <5 1>;
-				reg = <0>;
+				reg = <0x0>;
 				device_type = "ethernet-phy";
 			};
 			phy1: ethernet-phy@1 {
 				interrupt-parent = <&mpic>;
 				interrupts = <5 1>;
-				reg = <1>;
+				reg = <0x1>;
 				device_type = "ethernet-phy";
 			};
 			phy2: ethernet-phy@2 {
 				interrupt-parent = <&mpic>;
 				interrupts = <5 1>;
-				reg = <2>;
+				reg = <0x2>;
 				device_type = "ethernet-phy";
 			};
 			phy3: ethernet-phy@3 {
 				interrupt-parent = <&mpic>;
 				interrupts = <5 1>;
-				reg = <3>;
+				reg = <0x3>;
 				device_type = "ethernet-phy";
 			};
 		};
@@ -135,9 +136,9 @@
 			device_type = "network";
 			model = "eTSEC";
 			compatible = "gianfar";
-			reg = <24000 1000>;
+			reg = <0x24000 0x1000>;
 			local-mac-address = [ 00 00 00 00 00 00 ];
-			interrupts = <1d 2 1e 2 22 2>;
+			interrupts = <29 2 30 2 34 2>;
 			interrupt-parent = <&mpic>;
 			phy-handle = <&phy0>;
 		};
@@ -147,9 +148,9 @@
 			device_type = "network";
 			model = "eTSEC";
 			compatible = "gianfar";
-			reg = <25000 1000>;
+			reg = <0x25000 0x1000>;
 			local-mac-address = [ 00 00 00 00 00 00 ];
-			interrupts = <23 2 24 2 28 2>;
+			interrupts = <35 2 36 2 40 2>;
 			interrupt-parent = <&mpic>;
 			phy-handle = <&phy1>;
 		};
@@ -160,9 +161,9 @@
 			device_type = "network";
 			model = "eTSEC";
 			compatible = "gianfar";
-			reg = <26000 1000>;
+			reg = <0x26000 0x1000>;
 			local-mac-address = [ 00 00 00 00 00 00 ];
-			interrupts = <1f 2 20 2 21 2>;
+			interrupts = <31 2 32 2 33 2>;
 			interrupt-parent = <&mpic>;
 			phy-handle = <&phy2>;
 		};
@@ -172,9 +173,9 @@
 			device_type = "network";
 			model = "eTSEC";
 			compatible = "gianfar";
-			reg = <27000 1000>;
+			reg = <0x27000 0x1000>;
 			local-mac-address = [ 00 00 00 00 00 00 ];
-			interrupts = <25 2 26 2 27 2>;
+			interrupts = <37 2 38 2 39 2>;
 			interrupt-parent = <&mpic>;
 			phy-handle = <&phy3>;
 		};
@@ -184,9 +185,9 @@
 			cell-index = <0>;
 			device_type = "serial";
 			compatible = "ns16550";
-			reg = <4500 100>;	// reg base, size
+			reg = <0x4500 0x100>;	// reg base, size
 			clock-frequency = <0>;	// should we fill in in uboot?
-			interrupts = <2a 2>;
+			interrupts = <42 2>;
 			interrupt-parent = <&mpic>;
 		};
 
@@ -194,15 +195,15 @@
 			cell-index = <1>;
 			device_type = "serial";
 			compatible = "ns16550";
-			reg = <4600 100>;	// reg base, size
+			reg = <0x4600 0x100>;	// reg base, size
 			clock-frequency = <0>;	// should we fill in in uboot?
-			interrupts = <2a 2>;
+			interrupts = <42 2>;
 			interrupt-parent = <&mpic>;
 		};
 
 		global-utilities@e0000 {	//global utilities reg
 			compatible = "fsl,mpc8548-guts";
-			reg = <e0000 1000>;
+			reg = <0xe0000 0x1000>;
 			fsl,has-rstcr;
 		};
 
@@ -211,7 +212,7 @@
 			interrupt-controller;
 			#address-cells = <0>;
 			#interrupt-cells = <2>;
-			reg = <40000 40000>;
+			reg = <0x40000 0x40000>;
 			compatible = "chrp,open-pic";
 			device_type = "open-pic";
                         big-endian;
@@ -220,139 +221,139 @@
 
 	pci0: pci@e0008000 {
 		cell-index = <0>;
-		interrupt-map-mask = <f800 0 0 7>;
+		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 		interrupt-map = <
 			/* IDSEL 0x4 (PCIX Slot 2) */
-			02000 0 0 1 &mpic 0 1
-			02000 0 0 2 &mpic 1 1
-			02000 0 0 3 &mpic 2 1
-			02000 0 0 4 &mpic 3 1
+			0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
+			0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
+			0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
+			0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
 
 			/* IDSEL 0x5 (PCIX Slot 3) */
-			02800 0 0 1 &mpic 1 1
-			02800 0 0 2 &mpic 2 1
-			02800 0 0 3 &mpic 3 1
-			02800 0 0 4 &mpic 0 1
+			0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
+			0x2800 0x0 0x0 0x2 &mpic 0x2 0x1
+			0x2800 0x0 0x0 0x3 &mpic 0x3 0x1
+			0x2800 0x0 0x0 0x4 &mpic 0x0 0x1
 
 			/* IDSEL 0x6 (PCIX Slot 4) */
-			03000 0 0 1 &mpic 2 1
-			03000 0 0 2 &mpic 3 1
-			03000 0 0 3 &mpic 0 1
-			03000 0 0 4 &mpic 1 1
+			0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
+			0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
+			0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
+			0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
 
 			/* IDSEL 0x8 (PCIX Slot 5) */
-			04000 0 0 1 &mpic 0 1
-			04000 0 0 2 &mpic 1 1
-			04000 0 0 3 &mpic 2 1
-			04000 0 0 4 &mpic 3 1
+			0x4000 0x0 0x0 0x1 &mpic 0x0 0x1
+			0x4000 0x0 0x0 0x2 &mpic 0x1 0x1
+			0x4000 0x0 0x0 0x3 &mpic 0x2 0x1
+			0x4000 0x0 0x0 0x4 &mpic 0x3 0x1
 
 			/* IDSEL 0xC (Tsi310 bridge) */
-			06000 0 0 1 &mpic 0 1
-			06000 0 0 2 &mpic 1 1
-			06000 0 0 3 &mpic 2 1
-			06000 0 0 4 &mpic 3 1
+			0x6000 0x0 0x0 0x1 &mpic 0x0 0x1
+			0x6000 0x0 0x0 0x2 &mpic 0x1 0x1
+			0x6000 0x0 0x0 0x3 &mpic 0x2 0x1
+			0x6000 0x0 0x0 0x4 &mpic 0x3 0x1
 
 			/* IDSEL 0x14 (Slot 2) */
-			0a000 0 0 1 &mpic 0 1
-			0a000 0 0 2 &mpic 1 1
-			0a000 0 0 3 &mpic 2 1
-			0a000 0 0 4 &mpic 3 1
+			0xa000 0x0 0x0 0x1 &mpic 0x0 0x1
+			0xa000 0x0 0x0 0x2 &mpic 0x1 0x1
+			0xa000 0x0 0x0 0x3 &mpic 0x2 0x1
+			0xa000 0x0 0x0 0x4 &mpic 0x3 0x1
 
 			/* IDSEL 0x15 (Slot 3) */
-			0a800 0 0 1 &mpic 1 1
-			0a800 0 0 2 &mpic 2 1
-			0a800 0 0 3 &mpic 3 1
-			0a800 0 0 4 &mpic 0 1
+			0xa800 0x0 0x0 0x1 &mpic 0x1 0x1
+			0xa800 0x0 0x0 0x2 &mpic 0x2 0x1
+			0xa800 0x0 0x0 0x3 &mpic 0x3 0x1
+			0xa800 0x0 0x0 0x4 &mpic 0x0 0x1
 
 			/* IDSEL 0x16 (Slot 4) */
-			0b000 0 0 1 &mpic 2 1
-			0b000 0 0 2 &mpic 3 1
-			0b000 0 0 3 &mpic 0 1
-			0b000 0 0 4 &mpic 1 1
+			0xb000 0x0 0x0 0x1 &mpic 0x2 0x1
+			0xb000 0x0 0x0 0x2 &mpic 0x3 0x1
+			0xb000 0x0 0x0 0x3 &mpic 0x0 0x1
+			0xb000 0x0 0x0 0x4 &mpic 0x1 0x1
 
 			/* IDSEL 0x18 (Slot 5) */
-			0c000 0 0 1 &mpic 0 1
-			0c000 0 0 2 &mpic 1 1
-			0c000 0 0 3 &mpic 2 1
-			0c000 0 0 4 &mpic 3 1
+			0xc000 0x0 0x0 0x1 &mpic 0x0 0x1
+			0xc000 0x0 0x0 0x2 &mpic 0x1 0x1
+			0xc000 0x0 0x0 0x3 &mpic 0x2 0x1
+			0xc000 0x0 0x0 0x4 &mpic 0x3 0x1
 
 			/* IDSEL 0x1C (Tsi310 bridge PCI primary) */
-			0E000 0 0 1 &mpic 0 1
-			0E000 0 0 2 &mpic 1 1
-			0E000 0 0 3 &mpic 2 1
-			0E000 0 0 4 &mpic 3 1>;
+			0xe000 0x0 0x0 0x1 &mpic 0x0 0x1
+			0xe000 0x0 0x0 0x2 &mpic 0x1 0x1
+			0xe000 0x0 0x0 0x3 &mpic 0x2 0x1
+			0xe000 0x0 0x0 0x4 &mpic 0x3 0x1>;
 
 		interrupt-parent = <&mpic>;
-		interrupts = <18 2>;
+		interrupts = <24 2>;
 		bus-range = <0 0>;
-		ranges = <02000000 0 80000000 80000000 0 10000000
-			  01000000 0 00000000 e2000000 0 00800000>;
-		clock-frequency = <3f940aa>;
+		ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x10000000
+			  0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
+		clock-frequency = <66666666>;
 		#interrupt-cells = <1>;
 		#size-cells = <2>;
 		#address-cells = <3>;
-		reg = <e0008000 1000>;
+		reg = <0xe0008000 0x1000>;
 		compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
 		device_type = "pci";
 
 		pci_bridge@1c {
-			interrupt-map-mask = <f800 0 0 7>;
+			interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 			interrupt-map = <
 
 				/* IDSEL 0x00 (PrPMC Site) */
-				0000 0 0 1 &mpic 0 1
-				0000 0 0 2 &mpic 1 1
-				0000 0 0 3 &mpic 2 1
-				0000 0 0 4 &mpic 3 1
+				0000 0x0 0x0 0x1 &mpic 0x0 0x1
+				0000 0x0 0x0 0x2 &mpic 0x1 0x1
+				0000 0x0 0x0 0x3 &mpic 0x2 0x1
+				0000 0x0 0x0 0x4 &mpic 0x3 0x1
 
 				/* IDSEL 0x04 (VIA chip) */
-				2000 0 0 1 &mpic 0 1
-				2000 0 0 2 &mpic 1 1
-				2000 0 0 3 &mpic 2 1
-				2000 0 0 4 &mpic 3 1
+				0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
+				0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
+				0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
+				0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
 
 				/* IDSEL 0x05 (8139) */
-				2800 0 0 1 &mpic 1 1
+				0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
 
 				/* IDSEL 0x06 (Slot 6) */
-				3000 0 0 1 &mpic 2 1
-				3000 0 0 2 &mpic 3 1
-				3000 0 0 3 &mpic 0 1
-				3000 0 0 4 &mpic 1 1
+				0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
+				0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
+				0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
+				0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
 
 				/* IDESL 0x07 (Slot 7) */
-				3800 0 0 1 &mpic 3 1
-				3800 0 0 2 &mpic 0 1
-				3800 0 0 3 &mpic 1 1
-				3800 0 0 4 &mpic 2 1>;
+				0x3800 0x0 0x0 0x1 &mpic 0x3 0x1
+				0x3800 0x0 0x0 0x2 &mpic 0x0 0x1
+				0x3800 0x0 0x0 0x3 &mpic 0x1 0x1
+				0x3800 0x0 0x0 0x4 &mpic 0x2 0x1>;
 
-			reg = <e000 0 0 0 0>;
+			reg = <0xe000 0x0 0x0 0x0 0x0>;
 			#interrupt-cells = <1>;
 			#size-cells = <2>;
 			#address-cells = <3>;
-			ranges = <02000000 0 80000000
-				  02000000 0 80000000
-				  0 20000000
-				  01000000 0 00000000
-				  01000000 0 00000000
-				  0 00080000>;
-			clock-frequency = <1fca055>;
+			ranges = <0x2000000 0x0 0x80000000
+				  0x2000000 0x0 0x80000000
+				  0x0 0x20000000
+				  0x1000000 0x0 0x0
+				  0x1000000 0x0 0x0
+				  0x0 0x80000>;
+			clock-frequency = <33333333>;
 
 			isa@4 {
 				device_type = "isa";
 				#interrupt-cells = <2>;
 				#size-cells = <1>;
 				#address-cells = <2>;
-				reg = <2000 0 0 0 0>;
-				ranges = <1 0 01000000 0 0 00001000>;
+				reg = <0x2000 0x0 0x0 0x0 0x0>;
+				ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>;
 				interrupt-parent = <&i8259>;
 
 				i8259: interrupt-controller@20 {
 					interrupt-controller;
 					device_type = "interrupt-controller";
-					reg = <1 20 2
-					       1 a0 2
-					       1 4d0 2>;
+					reg = <0x1 0x20 0x2
+					       0x1 0xa0 0x2
+					       0x1 0x4d0 0x2>;
 					#address-cells = <0>;
 					#interrupt-cells = <2>;
 					compatible = "chrp,iic";
@@ -362,7 +363,7 @@
 
 				rtc@70 {
 					compatible = "pnpPNP,b00";
-					reg = <1 70 2>;
+					reg = <0x1 0x70 0x2>;
 				};
 			};
 		};
@@ -370,64 +371,64 @@
 
 	pci1: pci@e0009000 {
 		cell-index = <1>;
-		interrupt-map-mask = <f800 0 0 7>;
+		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 		interrupt-map = <
 
 			/* IDSEL 0x15 */
-			a800 0 0 1 &mpic b 1
-			a800 0 0 2 &mpic 1 1
-			a800 0 0 3 &mpic 2 1
-			a800 0 0 4 &mpic 3 1>;
+			0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
+			0xa800 0x0 0x0 0x2 &mpic 0x1 0x1
+			0xa800 0x0 0x0 0x3 &mpic 0x2 0x1
+			0xa800 0x0 0x0 0x4 &mpic 0x3 0x1>;
 
 		interrupt-parent = <&mpic>;
-		interrupts = <19 2>;
+		interrupts = <25 2>;
 		bus-range = <0 0>;
-		ranges = <02000000 0 90000000 90000000 0 10000000
-			  01000000 0 00000000 e2800000 0 00800000>;
-		clock-frequency = <3f940aa>;
+		ranges = <0x2000000 0x0 0x90000000 0x90000000 0x0 0x10000000
+			  0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
+		clock-frequency = <66666666>;
 		#interrupt-cells = <1>;
 		#size-cells = <2>;
 		#address-cells = <3>;
-		reg = <e0009000 1000>;
+		reg = <0xe0009000 0x1000>;
 		compatible = "fsl,mpc8540-pci";
 		device_type = "pci";
 	};
 
 	pci2: pcie@e000a000 {
 		cell-index = <2>;
-		interrupt-map-mask = <f800 0 0 7>;
+		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 		interrupt-map = <
 
 			/* IDSEL 0x0 (PEX) */
-			00000 0 0 1 &mpic 0 1
-			00000 0 0 2 &mpic 1 1
-			00000 0 0 3 &mpic 2 1
-			00000 0 0 4 &mpic 3 1>;
+			00000 0x0 0x0 0x1 &mpic 0x0 0x1
+			00000 0x0 0x0 0x2 &mpic 0x1 0x1
+			00000 0x0 0x0 0x3 &mpic 0x2 0x1
+			00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
 
 		interrupt-parent = <&mpic>;
-		interrupts = <1a 2>;
-		bus-range = <0 ff>;
-		ranges = <02000000 0 a0000000 a0000000 0 20000000
-			  01000000 0 00000000 e3000000 0 08000000>;
-		clock-frequency = <1fca055>;
+		interrupts = <26 2>;
+		bus-range = <0 255>;
+		ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
+			  0x1000000 0x0 0x0 0xe3000000 0x0 0x8000000>;
+		clock-frequency = <33333333>;
 		#interrupt-cells = <1>;
 		#size-cells = <2>;
 		#address-cells = <3>;
-		reg = <e000a000 1000>;
+		reg = <0xe000a000 0x1000>;
 		compatible = "fsl,mpc8548-pcie";
 		device_type = "pci";
 		pcie@0 {
-			reg = <0 0 0 0 0>;
+			reg = <0x0 0x0 0x0 0x0 0x0>;
 			#size-cells = <2>;
 			#address-cells = <3>;
 			device_type = "pci";
-			ranges = <02000000 0 a0000000
-				  02000000 0 a0000000
-				  0 20000000
+			ranges = <0x2000000 0x0 0xa0000000
+				  0x2000000 0x0 0xa0000000
+				  0x0 0x20000000
 
-				  01000000 0 00000000
-				  01000000 0 00000000
-				  0 08000000>;
+				  0x1000000 0x0 0x0
+				  0x1000000 0x0 0x0
+				  0x0 0x8000000>;
 		};
 	};
 };

arch/powerpc/boot/dts/mpc8555cds.dts

@@ -1,7 +1,7 @@
 /*
  * MPC8555 CDS Device Tree Source
  *
- * Copyright 2006 Freescale Semiconductor Inc.
+ * Copyright 2006, 2008 Freescale Semiconductor Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -9,6 +9,7 @@
  * option) any later version.
  */
 
+/dts-v1/;
 
 / {
 	model = "MPC8555CDS";
@@ -31,11 +32,11 @@
 
 		PowerPC,8555@0 {
 			device_type = "cpu";
-			reg = <0>;
-			d-cache-line-size = <20>;	// 32 bytes
-			i-cache-line-size = <20>;	// 32 bytes
-			d-cache-size = <8000>;		// L1, 32K
-			i-cache-size = <8000>;		// L1, 32K
+			reg = <0x0>;
+			d-cache-line-size = <32>;	// 32 bytes
+			i-cache-line-size = <32>;	// 32 bytes
+			d-cache-size = <0x8000>;		// L1, 32K
+			i-cache-size = <0x8000>;		// L1, 32K
 			timebase-frequency = <0>;	//  33 MHz, from uboot
 			bus-frequency = <0>;	// 166 MHz
 			clock-frequency = <0>;	// 825 MHz, from uboot
@@ -44,31 +45,31 @@
 
 	memory {
 		device_type = "memory";
-		reg = <00000000 08000000>;	// 128M at 0x0
+		reg = <0x0 0x8000000>;	// 128M at 0x0
 	};
 
 	soc8555@e0000000 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		device_type = "soc";
-		ranges = <0 e0000000 00100000>;
-		reg = <e0000000 00001000>;	// CCSRBAR 1M
+		ranges = <0x0 0xe0000000 0x100000>;
+		reg = <0xe0000000 0x1000>;	// CCSRBAR 1M
 		bus-frequency = <0>;
 
 		memory-controller@2000 {
 			compatible = "fsl,8555-memory-controller";
-			reg = <2000 1000>;
+			reg = <0x2000 0x1000>;
 			interrupt-parent = <&mpic>;
-			interrupts = <12 2>;
+			interrupts = <18 2>;
 		};
 
 		l2-cache-controller@20000 {
 			compatible = "fsl,8555-l2-cache-controller";
-			reg = <20000 1000>;
-			cache-line-size = <20>;	// 32 bytes
-			cache-size = <40000>;	// L2, 256K
+			reg = <0x20000 0x1000>;
+			cache-line-size = <32>;	// 32 bytes
+			cache-size = <0x40000>;	// L2, 256K
 			interrupt-parent = <&mpic>;
-			interrupts = <10 2>;
+			interrupts = <16 2>;
 		};
 
 		i2c@3000 {
@@ -76,8 +77,8 @@
 			#size-cells = <0>;
 			cell-index = <0>;
 			compatible = "fsl-i2c";
-			reg = <3000 100>;
-			interrupts = <2b 2>;
+			reg = <0x3000 0x100>;
+			interrupts = <43 2>;
 			interrupt-parent = <&mpic>;
 			dfsrr;
 		};
@@ -86,18 +87,18 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			compatible = "fsl,gianfar-mdio";
-			reg = <24520 20>;
+			reg = <0x24520 0x20>;
 
 			phy0: ethernet-phy@0 {
 				interrupt-parent = <&mpic>;
 				interrupts = <5 1>;
-				reg = <0>;
+				reg = <0x0>;
 				device_type = "ethernet-phy";
 			};
 			phy1: ethernet-phy@1 {
 				interrupt-parent = <&mpic>;
 				interrupts = <5 1>;
-				reg = <1>;
+				reg = <0x1>;
 				device_type = "ethernet-phy";
 			};
 		};
@@ -107,9 +108,9 @@
 			device_type = "network";
 			model = "TSEC";
 			compatible = "gianfar";
-			reg = <24000 1000>;
+			reg = <0x24000 0x1000>;
 			local-mac-address = [ 00 00 00 00 00 00 ];
-			interrupts = <1d 2 1e 2 22 2>;
+			interrupts = <29 2 30 2 34 2>;
 			interrupt-parent = <&mpic>;
 			phy-handle = <&phy0>;
 		};
@@ -119,9 +120,9 @@
 			device_type = "network";
 			model = "TSEC";
 			compatible = "gianfar";
-			reg = <25000 1000>;
+			reg = <0x25000 0x1000>;
 			local-mac-address = [ 00 00 00 00 00 00 ];
-			interrupts = <23 2 24 2 28 2>;
+			interrupts = <35 2 36 2 40 2>;
 			interrupt-parent = <&mpic>;
 			phy-handle = <&phy1>;
 		};
@@ -130,9 +131,9 @@
 			cell-index = <0>;
 			device_type = "serial";
 			compatible = "ns16550";
-			reg = <4500 100>; 	// reg base, size
+			reg = <0x4500 0x100>; 	// reg base, size
 			clock-frequency = <0>; 	// should we fill in in uboot?
-			interrupts = <2a 2>;
+			interrupts = <42 2>;
 			interrupt-parent = <&mpic>;
 		};
 
@@ -140,9 +141,9 @@
 			cell-index = <1>;
 			device_type = "serial";
 			compatible = "ns16550";
-			reg = <4600 100>;	// reg base, size
+			reg = <0x4600 0x100>;	// reg base, size
 			clock-frequency = <0>; 	// should we fill in in uboot?
-			interrupts = <2a 2>;
+			interrupts = <42 2>;
 			interrupt-parent = <&mpic>;
 		};
 
@@ -151,7 +152,7 @@
 			interrupt-controller;
 			#address-cells = <0>;
 			#interrupt-cells = <2>;
-			reg = <40000 40000>;
+			reg = <0x40000 0x40000>;
 			compatible = "chrp,open-pic";
 			device_type = "open-pic";
                         big-endian;
@@ -161,17 +162,17 @@
 			#address-cells = <1>;
 			#size-cells = <1>;
 			compatible = "fsl,mpc8555-cpm", "fsl,cpm2";
-			reg = <919c0 30>;
+			reg = <0x919c0 0x30>;
 			ranges;
 
 			muram@80000 {
 				#address-cells = <1>;
 				#size-cells = <1>;
-				ranges = <0 80000 10000>;
+				ranges = <0x0 0x80000 0x10000>;
 
 				data@0 {
 					compatible = "fsl,cpm-muram-data";
-					reg = <0 2000 9000 1000>;
+					reg = <0x0 0x2000 0x9000 0x1000>;
 				};
 			};
 
@@ -179,16 +180,16 @@
 				compatible = "fsl,mpc8555-brg",
 				             "fsl,cpm2-brg",
 				             "fsl,cpm-brg";
-				reg = <919f0 10 915f0 10>;
+				reg = <0x919f0 0x10 0x915f0 0x10>;
 			};
 
 			cpmpic: pic@90c00 {
 				interrupt-controller;
 				#address-cells = <0>;
 				#interrupt-cells = <2>;
-				interrupts = <2e 2>;
+				interrupts = <46 2>;
 				interrupt-parent = <&mpic>;
-				reg = <90c00 80>;
+				reg = <0x90c00 0x80>;
 				compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic";
 			};
 		};
@@ -196,68 +197,68 @@
 
 	pci0: pci@e0008000 {
 		cell-index = <0>;
-		interrupt-map-mask = <1f800 0 0 7>;
+		interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
 		interrupt-map = <
 
 			/* IDSEL 0x10 */
-			08000 0 0 1 &mpic 0 1
-			08000 0 0 2 &mpic 1 1
-			08000 0 0 3 &mpic 2 1
-			08000 0 0 4 &mpic 3 1
+			0x8000 0x0 0x0 0x1 &mpic 0x0 0x1
+			0x8000 0x0 0x0 0x2 &mpic 0x1 0x1
+			0x8000 0x0 0x0 0x3 &mpic 0x2 0x1
+			0x8000 0x0 0x0 0x4 &mpic 0x3 0x1
 
 			/* IDSEL 0x11 */
-			08800 0 0 1 &mpic 0 1
-			08800 0 0 2 &mpic 1 1
-			08800 0 0 3 &mpic 2 1
-			08800 0 0 4 &mpic 3 1
+			0x8800 0x0 0x0 0x1 &mpic 0x0 0x1
+			0x8800 0x0 0x0 0x2 &mpic 0x1 0x1
+			0x8800 0x0 0x0 0x3 &mpic 0x2 0x1
+			0x8800 0x0 0x0 0x4 &mpic 0x3 0x1
 
 			/* IDSEL 0x12 (Slot 1) */
-			09000 0 0 1 &mpic 0 1
-			09000 0 0 2 &mpic 1 1
-			09000 0 0 3 &mpic 2 1
-			09000 0 0 4 &mpic 3 1
+			0x9000 0x0 0x0 0x1 &mpic 0x0 0x1
+			0x9000 0x0 0x0 0x2 &mpic 0x1 0x1
+			0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
+			0x9000 0x0 0x0 0x4 &mpic 0x3 0x1
 
 			/* IDSEL 0x13 (Slot 2) */
-			09800 0 0 1 &mpic 1 1
-			09800 0 0 2 &mpic 2 1
-			09800 0 0 3 &mpic 3 1
-			09800 0 0 4 &mpic 0 1
+			0x9800 0x0 0x0 0x1 &mpic 0x1 0x1
+			0x9800 0x0 0x0 0x2 &mpic 0x2 0x1
+			0x9800 0x0 0x0 0x3 &mpic 0x3 0x1
+			0x9800 0x0 0x0 0x4 &mpic 0x0 0x1
 
 			/* IDSEL 0x14 (Slot 3) */
-			0a000 0 0 1 &mpic 2 1
-			0a000 0 0 2 &mpic 3 1
-			0a000 0 0 3 &mpic 0 1
-			0a000 0 0 4 &mpic 1 1
+			0xa000 0x0 0x0 0x1 &mpic 0x2 0x1
+			0xa000 0x0 0x0 0x2 &mpic 0x3 0x1
+			0xa000 0x0 0x0 0x3 &mpic 0x0 0x1
+			0xa000 0x0 0x0 0x4 &mpic 0x1 0x1
 
 			/* IDSEL 0x15 (Slot 4) */
-			0a800 0 0 1 &mpic 3 1
-			0a800 0 0 2 &mpic 0 1
-			0a800 0 0 3 &mpic 1 1
-			0a800 0 0 4 &mpic 2 1
+			0xa800 0x0 0x0 0x1 &mpic 0x3 0x1
+			0xa800 0x0 0x0 0x2 &mpic 0x0 0x1
+			0xa800 0x0 0x0 0x3 &mpic 0x1 0x1
+			0xa800 0x0 0x0 0x4 &mpic 0x2 0x1
 
 			/* Bus 1 (Tundra Bridge) */
 			/* IDSEL 0x12 (ISA bridge) */
-			19000 0 0 1 &mpic 0 1
-			19000 0 0 2 &mpic 1 1
-			19000 0 0 3 &mpic 2 1
-			19000 0 0 4 &mpic 3 1>;
+			0x19000 0x0 0x0 0x1 &mpic 0x0 0x1
+			0x19000 0x0 0x0 0x2 &mpic 0x1 0x1
+			0x19000 0x0 0x0 0x3 &mpic 0x2 0x1
+			0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>;
 		interrupt-parent = <&mpic>;
-		interrupts = <18 2>;
+		interrupts = <24 2>;
 		bus-range = <0 0>;
-		ranges = <02000000 0 80000000 80000000 0 20000000
-			  01000000 0 00000000 e2000000 0 00100000>;
-		clock-frequency = <3f940aa>;
+		ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
+			  0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
+		clock-frequency = <66666666>;
 		#interrupt-cells = <1>;
 		#size-cells = <2>;
 		#address-cells = <3>;
-		reg = <e0008000 1000>;
+		reg = <0xe0008000 0x1000>;
 		compatible = "fsl,mpc8540-pci";
 		device_type = "pci";
 
 		i8259@19000 {
 			interrupt-controller;
 			device_type = "interrupt-controller";
-			reg = <19000 0 0 0 1>;
+			reg = <0x19000 0x0 0x0 0x0 0x1>;
 			#address-cells = <0>;
 			#interrupt-cells = <2>;
 			compatible = "chrp,iic";
@@ -268,24 +269,24 @@
 
 	pci1: pci@e0009000 {
 		cell-index = <1>;
-		interrupt-map-mask = <f800 0 0 7>;
+		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 		interrupt-map = <
 
 			/* IDSEL 0x15 */
-			a800 0 0 1 &mpic b 1
-			a800 0 0 2 &mpic b 1
-			a800 0 0 3 &mpic b 1
-			a800 0 0 4 &mpic b 1>;
+			0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
+			0xa800 0x0 0x0 0x2 &mpic 0xb 0x1
+			0xa800 0x0 0x0 0x3 &mpic 0xb 0x1
+			0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>;
 		interrupt-parent = <&mpic>;
-		interrupts = <19 2>;
+		interrupts = <25 2>;
 		bus-range = <0 0>;
-		ranges = <02000000 0 a0000000 a0000000 0 20000000
-			  01000000 0 00000000 e3000000 0 00100000>;
-		clock-frequency = <3f940aa>;
+		ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
+			  0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
+		clock-frequency = <66666666>;
 		#interrupt-cells = <1>;
 		#size-cells = <2>;
 		#address-cells = <3>;
-		reg = <e0009000 1000>;
+		reg = <0xe0009000 0x1000>;
 		compatible = "fsl,mpc8540-pci";
 		device_type = "pci";
 	};

arch/powerpc/boot/dts/mpc8560ads.dts

@@ -1,7 +1,7 @@
 /*
  * MPC8560 ADS Device Tree Source
  *
- * Copyright 2006 Freescale Semiconductor Inc.
+ * Copyright 2006, 2008 Freescale Semiconductor Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -9,6 +9,7 @@
  * option) any later version.
  */
 
+/dts-v1/;
 
 / {
 	model = "MPC8560ADS";
@@ -32,74 +33,74 @@
 
 		PowerPC,8560@0 {
 			device_type = "cpu";
-			reg = <0>;
-			d-cache-line-size = <20>;	// 32 bytes
-			i-cache-line-size = <20>;	// 32 bytes
-			d-cache-size = <8000>;		// L1, 32K
-			i-cache-size = <8000>;		// L1, 32K
-			timebase-frequency = <04ead9a0>;
-			bus-frequency = <13ab6680>;
-			clock-frequency = <312c8040>;
+			reg = <0x0>;
+			d-cache-line-size = <32>;	// 32 bytes
+			i-cache-line-size = <32>;	// 32 bytes
+			d-cache-size = <0x8000>;		// L1, 32K
+			i-cache-size = <0x8000>;		// L1, 32K
+			timebase-frequency = <82500000>;
+			bus-frequency = <330000000>;
+			clock-frequency = <825000000>;
 		};
 	};
 
 	memory {
 		device_type = "memory";
-		reg = <00000000 10000000>;
+		reg = <0x0 0x10000000>;
 	};
 
 	soc8560@e0000000 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		device_type = "soc";
-		ranges = <0 e0000000 00100000>;
-		reg = <e0000000 00000200>;
-		bus-frequency = <13ab6680>;
+		ranges = <0x0 0xe0000000 0x100000>;
+		reg = <0xe0000000 0x200>;
+		bus-frequency = <330000000>;
 
 		memory-controller@2000 {
 			compatible = "fsl,8540-memory-controller";
-			reg = <2000 1000>;
+			reg = <0x2000 0x1000>;
 			interrupt-parent = <&mpic>;
-			interrupts = <12 2>;
+			interrupts = <18 2>;
 		};
 
 		l2-cache-controller@20000 {
 			compatible = "fsl,8540-l2-cache-controller";
-			reg = <20000 1000>;
-			cache-line-size = <20>;	// 32 bytes
-			cache-size = <40000>;	// L2, 256K
+			reg = <0x20000 0x1000>;
+			cache-line-size = <32>;	// 32 bytes
+			cache-size = <0x40000>;	// L2, 256K
 			interrupt-parent = <&mpic>;
-			interrupts = <10 2>;
+			interrupts = <16 2>;
 		};
 
 		mdio@24520 {
 			#address-cells = <1>;
 			#size-cells = <0>;
 			compatible = "fsl,gianfar-mdio";
-			reg = <24520 20>;
+			reg = <0x24520 0x20>;
 
 			phy0: ethernet-phy@0 {
 				interrupt-parent = <&mpic>;
 				interrupts = <5 1>;
-				reg = <0>;
+				reg = <0x0>;
 				device_type = "ethernet-phy";
 			};
 			phy1: ethernet-phy@1 {
 				interrupt-parent = <&mpic>;
 				interrupts = <5 1>;
-				reg = <1>;
+				reg = <0x1>;
 				device_type = "ethernet-phy";
 			};
 			phy2: ethernet-phy@2 {
 				interrupt-parent = <&mpic>;
 				interrupts = <7 1>;
-				reg = <2>;
+				reg = <0x2>;
 				device_type = "ethernet-phy";
 			};
 			phy3: ethernet-phy@3 {
 				interrupt-parent = <&mpic>;
 				interrupts = <7 1>;
-				reg = <3>;
+				reg = <0x3>;
 				device_type = "ethernet-phy";
 			};
 		};
@@ -109,9 +110,9 @@
 			device_type = "network";
 			model = "TSEC";
 			compatible = "gianfar";
-			reg = <24000 1000>;
+			reg = <0x24000 0x1000>;
 			local-mac-address = [ 00 00 00 00 00 00 ];
-			interrupts = <1d 2 1e 2 22 2>;
+			interrupts = <29 2 30 2 34 2>;
 			interrupt-parent = <&mpic>;
 			phy-handle = <&phy0>;
 		};
@@ -121,9 +122,9 @@
 			device_type = "network";
 			model = "TSEC";
 			compatible = "gianfar";
-			reg = <25000 1000>;
+			reg = <0x25000 0x1000>;
 			local-mac-address = [ 00 00 00 00 00 00 ];
-			interrupts = <23 2 24 2 28 2>;
+			interrupts = <35 2 36 2 40 2>;
 			interrupt-parent = <&mpic>;
 			phy-handle = <&phy1>;
 		};
@@ -132,7 +133,7 @@
 			interrupt-controller;
 			#address-cells = <0>;
 			#interrupt-cells = <2>;
-			reg = <40000 40000>;
+			reg = <0x40000 0x40000>;
 			device_type = "open-pic";
 		};
 
@@ -140,17 +141,17 @@
 			#address-cells = <1>;
 			#size-cells = <1>;
 			compatible = "fsl,mpc8560-cpm", "fsl,cpm2";
-			reg = <919c0 30>;
+			reg = <0x919c0 0x30>;
 			ranges;
 
 			muram@80000 {
 				#address-cells = <1>;
 				#size-cells = <1>;
-				ranges = <0 80000 10000>;
+				ranges = <0x0 0x80000 0x10000>;
 
 				data@0 {
 					compatible = "fsl,cpm-muram-data";
-					reg = <0 4000 9000 2000>;
+					reg = <0x0 0x4000 0x9000 0x2000>;
 				};
 			};
 
@@ -158,17 +159,17 @@
 				compatible = "fsl,mpc8560-brg",
 				             "fsl,cpm2-brg",
 				             "fsl,cpm-brg";
-				reg = <919f0 10 915f0 10>;
-				clock-frequency = <d#165000000>;
+				reg = <0x919f0 0x10 0x915f0 0x10>;
+				clock-frequency = <165000000>;
 			};
 
 			cpmpic: pic@90c00 {
 				interrupt-controller;
 				#address-cells = <0>;
 				#interrupt-cells = <2>;
-				interrupts = <2e 2>;
+				interrupts = <46 2>;
 				interrupt-parent = <&mpic>;
-				reg = <90c00 80>;
+				reg = <0x90c00 0x80>;
 				compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
 			};
 
@@ -176,11 +177,11 @@
 				device_type = "serial";
 				compatible = "fsl,mpc8560-scc-uart",
 				             "fsl,cpm2-scc-uart";
-				reg = <91a00 20 88000 100>;
+				reg = <0x91a00 0x20 0x88000 0x100>;
 				fsl,cpm-brg = <1>;
-				fsl,cpm-command = <00800000>;
-				current-speed = <1c200>;
-				interrupts = <28 8>;
+				fsl,cpm-command = <0x800000>;
+				current-speed = <115200>;
+				interrupts = <40 8>;
 				interrupt-parent = <&cpmpic>;
 			};
 
@@ -188,11 +189,11 @@
 				device_type = "serial";
 				compatible = "fsl,mpc8560-scc-uart",
 				             "fsl,cpm2-scc-uart";
-				reg = <91a20 20 88100 100>;
+				reg = <0x91a20 0x20 0x88100 0x100>;
 				fsl,cpm-brg = <2>;
-				fsl,cpm-command = <04a00000>;
-				current-speed = <1c200>;
-				interrupts = <29 8>;
+				fsl,cpm-command = <0x4a00000>;
+				current-speed = <115200>;
+				interrupts = <41 8>;
 				interrupt-parent = <&cpmpic>;
 			};
 
@@ -200,10 +201,10 @@
 				device_type = "network";
 				compatible = "fsl,mpc8560-fcc-enet",
 				             "fsl,cpm2-fcc-enet";
-				reg = <91320 20 88500 100 913b0 1>;
+				reg = <0x91320 0x20 0x88500 0x100 0x913b0 0x1>;
 				local-mac-address = [ 00 00 00 00 00 00 ];
-				fsl,cpm-command = <16200300>;
-				interrupts = <21 8>;
+				fsl,cpm-command = <0x16200300>;
+				interrupts = <33 8>;
 				interrupt-parent = <&cpmpic>;
 				phy-handle = <&phy2>;
 			};
@@ -212,10 +213,10 @@
 				device_type = "network";
 				compatible = "fsl,mpc8560-fcc-enet",
 				             "fsl,cpm2-fcc-enet";
-				reg = <91340 20 88600 100 913d0 1>;
+				reg = <0x91340 0x20 0x88600 0x100 0x913d0 0x1>;
 				local-mac-address = [ 00 00 00 00 00 00 ];
-				fsl,cpm-command = <1a400300>;
-				interrupts = <22 8>;
+				fsl,cpm-command = <0x1a400300>;
+				interrupts = <34 8>;
 				interrupt-parent = <&cpmpic>;
 				phy-handle = <&phy3>;
 			};
@@ -229,87 +230,87 @@
 		#address-cells = <3>;
 		compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
 		device_type = "pci";
-		reg = <e0008000 1000>;
-		clock-frequency = <3f940aa>;
-		interrupt-map-mask = <f800 0 0 7>;
+		reg = <0xe0008000 0x1000>;
+		clock-frequency = <66666666>;
+		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 		interrupt-map = <
 
 				/* IDSEL 0x2 */
-				 1000 0 0 1 &mpic 1 1
-				 1000 0 0 2 &mpic 2 1
-				 1000 0 0 3 &mpic 3 1
-				 1000 0 0 4 &mpic 4 1
+				 0x1000 0x0 0x0 0x1 &mpic 0x1 0x1
+				 0x1000 0x0 0x0 0x2 &mpic 0x2 0x1
+				 0x1000 0x0 0x0 0x3 &mpic 0x3 0x1
+				 0x1000 0x0 0x0 0x4 &mpic 0x4 0x1
 
 				/* IDSEL 0x3 */
-				 1800 0 0 1 &mpic 4 1
-				 1800 0 0 2 &mpic 1 1
-				 1800 0 0 3 &mpic 2 1
-				 1800 0 0 4 &mpic 3 1
+				 0x1800 0x0 0x0 0x1 &mpic 0x4 0x1
+				 0x1800 0x0 0x0 0x2 &mpic 0x1 0x1
+				 0x1800 0x0 0x0 0x3 &mpic 0x2 0x1
+				 0x1800 0x0 0x0 0x4 &mpic 0x3 0x1
 
 				/* IDSEL 0x4 */
-				 2000 0 0 1 &mpic 3 1
-				 2000 0 0 2 &mpic 4 1
-				 2000 0 0 3 &mpic 1 1
-				 2000 0 0 4 &mpic 2 1
+				 0x2000 0x0 0x0 0x1 &mpic 0x3 0x1
+				 0x2000 0x0 0x0 0x2 &mpic 0x4 0x1
+				 0x2000 0x0 0x0 0x3 &mpic 0x1 0x1
+				 0x2000 0x0 0x0 0x4 &mpic 0x2 0x1
 
 				/* IDSEL 0x5  */
-				 2800 0 0 1 &mpic 2 1
-				 2800 0 0 2 &mpic 3 1
-				 2800 0 0 3 &mpic 4 1
-				 2800 0 0 4 &mpic 1 1
+				 0x2800 0x0 0x0 0x1 &mpic 0x2 0x1
+				 0x2800 0x0 0x0 0x2 &mpic 0x3 0x1
+				 0x2800 0x0 0x0 0x3 &mpic 0x4 0x1
+				 0x2800 0x0 0x0 0x4 &mpic 0x1 0x1
 
 				/* IDSEL 12 */
-				 6000 0 0 1 &mpic 1 1
-				 6000 0 0 2 &mpic 2 1
-				 6000 0 0 3 &mpic 3 1
-				 6000 0 0 4 &mpic 4 1
+				 0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
+				 0x6000 0x0 0x0 0x2 &mpic 0x2 0x1
+				 0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
+				 0x6000 0x0 0x0 0x4 &mpic 0x4 0x1
 
 				/* IDSEL 13 */
-				 6800 0 0 1 &mpic 4 1
-				 6800 0 0 2 &mpic 1 1
-				 6800 0 0 3 &mpic 2 1
-				 6800 0 0 4 &mpic 3 1
+				 0x6800 0x0 0x0 0x1 &mpic 0x4 0x1
+				 0x6800 0x0 0x0 0x2 &mpic 0x1 0x1
+				 0x6800 0x0 0x0 0x3 &mpic 0x2 0x1
+				 0x6800 0x0 0x0 0x4 &mpic 0x3 0x1
 
 				/* IDSEL 14*/
-				 7000 0 0 1 &mpic 3 1
-				 7000 0 0 2 &mpic 4 1
-				 7000 0 0 3 &mpic 1 1
-				 7000 0 0 4 &mpic 2 1
+				 0x7000 0x0 0x0 0x1 &mpic 0x3 0x1
+				 0x7000 0x0 0x0 0x2 &mpic 0x4 0x1
+				 0x7000 0x0 0x0 0x3 &mpic 0x1 0x1
+				 0x7000 0x0 0x0 0x4 &mpic 0x2 0x1
 
 				/* IDSEL 15 */
-				 7800 0 0 1 &mpic 2 1
-				 7800 0 0 2 &mpic 3 1
-				 7800 0 0 3 &mpic 4 1
-				 7800 0 0 4 &mpic 1 1
+				 0x7800 0x0 0x0 0x1 &mpic 0x2 0x1
+				 0x7800 0x0 0x0 0x2 &mpic 0x3 0x1
+				 0x7800 0x0 0x0 0x3 &mpic 0x4 0x1
+				 0x7800 0x0 0x0 0x4 &mpic 0x1 0x1
 
 				/* IDSEL 18 */
-				 9000 0 0 1 &mpic 1 1
-				 9000 0 0 2 &mpic 2 1
-				 9000 0 0 3 &mpic 3 1
-				 9000 0 0 4 &mpic 4 1
+				 0x9000 0x0 0x0 0x1 &mpic 0x1 0x1
+				 0x9000 0x0 0x0 0x2 &mpic 0x2 0x1
+				 0x9000 0x0 0x0 0x3 &mpic 0x3 0x1
+				 0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
 
 				/* IDSEL 19 */
-				 9800 0 0 1 &mpic 4 1
-				 9800 0 0 2 &mpic 1 1
-				 9800 0 0 3 &mpic 2 1
-				 9800 0 0 4 &mpic 3 1
+				 0x9800 0x0 0x0 0x1 &mpic 0x4 0x1
+				 0x9800 0x0 0x0 0x2 &mpic 0x1 0x1
+				 0x9800 0x0 0x0 0x3 &mpic 0x2 0x1
+				 0x9800 0x0 0x0 0x4 &mpic 0x3 0x1
 
 				/* IDSEL 20 */
-				 a000 0 0 1 &mpic 3 1
-				 a000 0 0 2 &mpic 4 1
-				 a000 0 0 3 &mpic 1 1
-				 a000 0 0 4 &mpic 2 1
+				 0xa000 0x0 0x0 0x1 &mpic 0x3 0x1
+				 0xa000 0x0 0x0 0x2 &mpic 0x4 0x1
+				 0xa000 0x0 0x0 0x3 &mpic 0x1 0x1
+				 0xa000 0x0 0x0 0x4 &mpic 0x2 0x1
 
 				/* IDSEL 21 */
-				 a800 0 0 1 &mpic 2 1
-				 a800 0 0 2 &mpic 3 1
-				 a800 0 0 3 &mpic 4 1
-				 a800 0 0 4 &mpic 1 1>;
+				 0xa800 0x0 0x0 0x1 &mpic 0x2 0x1
+				 0xa800 0x0 0x0 0x2 &mpic 0x3 0x1
+				 0xa800 0x0 0x0 0x3 &mpic 0x4 0x1
+				 0xa800 0x0 0x0 0x4 &mpic 0x1 0x1>;
 
 		interrupt-parent = <&mpic>;
-		interrupts = <18 2>;
+		interrupts = <24 2>;
 		bus-range = <0 0>;
-		ranges = <02000000 0 80000000 80000000 0 20000000
-			  01000000 0 00000000 e2000000 0 01000000>;
+		ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
+			  0x1000000 0x0 0x0 0xe2000000 0x0 0x1000000>;
 	};
 };

arch/powerpc/boot/dts/mpc8568mds.dts

@@ -1,7 +1,7 @@
 /*
  * MPC8568E MDS Device Tree Source
  *
- * Copyright 2007 Freescale Semiconductor Inc.
+ * Copyright 2007, 2008 Freescale Semiconductor Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -9,10 +9,7 @@
  * option) any later version.
  */
 
-
-/*
-/memreserve/	00000000 1000000;
-*/
+/dts-v1/;
 
 / {
 	model = "MPC8568EMDS";
@@ -37,11 +34,11 @@
 
 		PowerPC,8568@0 {
 			device_type = "cpu";
-			reg = <0>;
-			d-cache-line-size = <20>;	// 32 bytes
-			i-cache-line-size = <20>;	// 32 bytes
-			d-cache-size = <8000>;		// L1, 32K
-			i-cache-size = <8000>;		// L1, 32K
+			reg = <0x0>;
+			d-cache-line-size = <32>;	// 32 bytes
+			i-cache-line-size = <32>;	// 32 bytes
+			d-cache-size = <0x8000>;		// L1, 32K
+			i-cache-size = <0x8000>;		// L1, 32K
 			timebase-frequency = <0>;
 			bus-frequency = <0>;
 			clock-frequency = <0>;
@@ -50,36 +47,36 @@
 
 	memory {
 		device_type = "memory";
-		reg = <00000000 10000000>;
+		reg = <0x0 0x10000000>;
 	};
 
 	bcsr@f8000000 {
 		device_type = "board-control";
-		reg = <f8000000 8000>;
+		reg = <0xf8000000 0x8000>;
 	};
 
 	soc8568@e0000000 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		device_type = "soc";
-		ranges = <0 e0000000 00100000>;
-		reg = <e0000000 00001000>;
+		ranges = <0x0 0xe0000000 0x100000>;
+		reg = <0xe0000000 0x1000>;
 		bus-frequency = <0>;
 
 		memory-controller@2000 {
 			compatible = "fsl,8568-memory-controller";
-			reg = <2000 1000>;
+			reg = <0x2000 0x1000>;
 			interrupt-parent = <&mpic>;
-			interrupts = <12 2>;
+			interrupts = <18 2>;
 		};
 
 		l2-cache-controller@20000 {
 			compatible = "fsl,8568-l2-cache-controller";
-			reg = <20000 1000>;
-			cache-line-size = <20>;	// 32 bytes
-			cache-size = <80000>;	// L2, 512K
+			reg = <0x20000 0x1000>;
+			cache-line-size = <32>;	// 32 bytes
+			cache-size = <0x80000>;	// L2, 512K
 			interrupt-parent = <&mpic>;
-			interrupts = <10 2>;
+			interrupts = <16 2>;
 		};
 
 		i2c@3000 {
@@ -87,14 +84,14 @@
 			#size-cells = <0>;
 			cell-index = <0>;
 			compatible = "fsl-i2c";
-			reg = <3000 100>;
-			interrupts = <2b 2>;
+			reg = <0x3000 0x100>;
+			interrupts = <43 2>;
 			interrupt-parent = <&mpic>;
 			dfsrr;
 
 			rtc@68 {
 				compatible = "dallas,ds1374";
-				reg = <68>;
+				reg = <0x68>;
 			};
 		};
 
@@ -103,8 +100,8 @@
 			#size-cells = <0>;
 			cell-index = <1>;
 			compatible = "fsl-i2c";
-			reg = <3100 100>;
-			interrupts = <2b 2>;
+			reg = <0x3100 0x100>;
+			interrupts = <43 2>;
 			interrupt-parent = <&mpic>;
 			dfsrr;
 		};
@@ -113,30 +110,30 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			compatible = "fsl,gianfar-mdio";
-			reg = <24520 20>;
+			reg = <0x24520 0x20>;
 
 			phy0: ethernet-phy@7 {
 				interrupt-parent = <&mpic>;
 				interrupts = <1 1>;
-				reg = <7>;
+				reg = <0x7>;
 				device_type = "ethernet-phy";
 			};
 			phy1: ethernet-phy@1 {
 				interrupt-parent = <&mpic>;
 				interrupts = <2 1>;
-				reg = <1>;
+				reg = <0x1>;
 				device_type = "ethernet-phy";
 			};
 			phy2: ethernet-phy@2 {
 				interrupt-parent = <&mpic>;
 				interrupts = <1 1>;
-				reg = <2>;
+				reg = <0x2>;
 				device_type = "ethernet-phy";
 			};
 			phy3: ethernet-phy@3 {
 				interrupt-parent = <&mpic>;
 				interrupts = <2 1>;
-				reg = <3>;
+				reg = <0x3>;
 				device_type = "ethernet-phy";
 			};
 		};
@@ -146,9 +143,9 @@
 			device_type = "network";
 			model = "eTSEC";
 			compatible = "gianfar";
-			reg = <24000 1000>;
+			reg = <0x24000 0x1000>;
 			local-mac-address = [ 00 00 00 00 00 00 ];
- 			interrupts = <1d 2 1e 2 22 2>;
+ 			interrupts = <29 2 30 2 34 2>;
 			interrupt-parent = <&mpic>;
 			phy-handle = <&phy2>;
 		};
@@ -158,9 +155,9 @@
 			device_type = "network";
 			model = "eTSEC";
 			compatible = "gianfar";
-			reg = <25000 1000>;
+			reg = <0x25000 0x1000>;
 			local-mac-address = [ 00 00 00 00 00 00 ];
- 			interrupts = <23 2 24 2 28 2>;
+ 			interrupts = <35 2 36 2 40 2>;
 			interrupt-parent = <&mpic>;
 			phy-handle = <&phy3>;
 		};
@@ -169,15 +166,15 @@
 			cell-index = <0>;
 			device_type = "serial";
 			compatible = "ns16550";
-			reg = <4500 100>;
+			reg = <0x4500 0x100>;
 			clock-frequency = <0>;
-			interrupts = <2a 2>;
+			interrupts = <42 2>;
 			interrupt-parent = <&mpic>;
 		};
 
 		global-utilities@e0000 {	//global utilities block
 			compatible = "fsl,mpc8548-guts";
-			reg = <e0000 1000>;
+			reg = <0xe0000 0x1000>;
 			fsl,has-rstcr;
 		};
 
@@ -185,9 +182,9 @@
 			cell-index = <1>;
 			device_type = "serial";
 			compatible = "ns16550";
-			reg = <4600 100>;
+			reg = <0x4600 0x100>;
 			clock-frequency = <0>;
-			interrupts = <2a 2>;
+			interrupts = <42 2>;
 			interrupt-parent = <&mpic>;
 		};
 
@@ -195,13 +192,13 @@
 			device_type = "crypto";
 			model = "SEC2";
 			compatible = "talitos";
-			reg = <30000 f000>;
-			interrupts = <2d 2>;
+			reg = <0x30000 0xf000>;
+			interrupts = <45 2>;
 			interrupt-parent = <&mpic>;
 			num-channels = <4>;
-			channel-fifo-len = <18>;
-			exec-units-mask = <000000fe>;
-			descriptor-types-mask = <012b0ebf>;
+			channel-fifo-len = <24>;
+			exec-units-mask = <0xfe>;
+			descriptor-types-mask = <0x12b0ebf>;
 		};
 
 		mpic: pic@40000 {
@@ -209,73 +206,73 @@
 			interrupt-controller;
 			#address-cells = <0>;
 			#interrupt-cells = <2>;
-			reg = <40000 40000>;
+			reg = <0x40000 0x40000>;
 			compatible = "chrp,open-pic";
 			device_type = "open-pic";
                         big-endian;
 		};
 
 		par_io@e0100 {
-			reg = <e0100 100>;
+			reg = <0xe0100 0x100>;
 			device_type = "par_io";
 			num-ports = <7>;
 
 			pio1: ucc_pin@01 {
 				pio-map = <
 			/* port  pin  dir  open_drain  assignment  has_irq */
-					4  0a  1  0  2  0 	/* TxD0 */
-					4  09  1  0  2  0 	/* TxD1 */
-					4  08  1  0  2  0 	/* TxD2 */
-					4  07  1  0  2  0 	/* TxD3 */
-					4  17  1  0  2  0 	/* TxD4 */
-					4  16  1  0  2  0 	/* TxD5 */
-					4  15  1  0  2  0 	/* TxD6 */
-					4  14  1  0  2  0 	/* TxD7 */
-					4  0f  2  0  2  0 	/* RxD0 */
-					4  0e  2  0  2  0 	/* RxD1 */
-					4  0d  2  0  2  0 	/* RxD2 */
-					4  0c  2  0  2  0 	/* RxD3 */
-					4  1d  2  0  2  0 	/* RxD4 */
-					4  1c  2  0  2  0 	/* RxD5 */
-					4  1b  2  0  2  0 	/* RxD6 */
-					4  1a  2  0  2  0 	/* RxD7 */
-					4  0b  1  0  2  0 	/* TX_EN */
-					4  18  1  0  2  0 	/* TX_ER */
-					4  10  2  0  2  0 	/* RX_DV */
-					4  1e  2  0  2  0 	/* RX_ER */
-					4  11  2  0  2  0 	/* RX_CLK */
-					4  13  1  0  2  0 	/* GTX_CLK */
-					1  1f  2  0  3  0>;	/* GTX125 */
+					0x4  0xa  0x1  0x0  0x2  0x0 	/* TxD0 */
+					0x4  0x9  0x1  0x0  0x2  0x0 	/* TxD1 */
+					0x4  0x8  0x1  0x0  0x2  0x0 	/* TxD2 */
+					0x4  0x7  0x1  0x0  0x2  0x0 	/* TxD3 */
+					0x4  0x17  0x1  0x0  0x2  0x0 	/* TxD4 */
+					0x4  0x16  0x1  0x0  0x2  0x0 	/* TxD5 */
+					0x4  0x15  0x1  0x0  0x2  0x0 	/* TxD6 */
+					0x4  0x14  0x1  0x0  0x2  0x0 	/* TxD7 */
+					0x4  0xf  0x2  0x0  0x2  0x0 	/* RxD0 */
+					0x4  0xe  0x2  0x0  0x2  0x0 	/* RxD1 */
+					0x4  0xd  0x2  0x0  0x2  0x0 	/* RxD2 */
+					0x4  0xc  0x2  0x0  0x2  0x0 	/* RxD3 */
+					0x4  0x1d  0x2  0x0  0x2  0x0 	/* RxD4 */
+					0x4  0x1c  0x2  0x0  0x2  0x0 	/* RxD5 */
+					0x4  0x1b  0x2  0x0  0x2  0x0 	/* RxD6 */
+					0x4  0x1a  0x2  0x0  0x2  0x0 	/* RxD7 */
+					0x4  0xb  0x1  0x0  0x2  0x0 	/* TX_EN */
+					0x4  0x18  0x1  0x0  0x2  0x0 	/* TX_ER */
+					0x4  0x10  0x2  0x0  0x2  0x0 	/* RX_DV */
+					0x4  0x1e  0x2  0x0  0x2  0x0 	/* RX_ER */
+					0x4  0x11  0x2  0x0  0x2  0x0 	/* RX_CLK */
+					0x4  0x13  0x1  0x0  0x2  0x0 	/* GTX_CLK */
+					0x1  0x1f  0x2  0x0  0x3  0x0>;	/* GTX125 */
 			};
 
 			pio2: ucc_pin@02 {
 				pio-map = <
 			/* port  pin  dir  open_drain  assignment  has_irq */
-					5  0a 1  0  2  0   /* TxD0 */
-					5  09 1  0  2  0   /* TxD1 */
-					5  08 1  0  2  0   /* TxD2 */
-					5  07 1  0  2  0   /* TxD3 */
-					5  17 1  0  2  0   /* TxD4 */
-					5  16 1  0  2  0   /* TxD5 */
-					5  15 1  0  2  0   /* TxD6 */
-					5  14 1  0  2  0   /* TxD7 */
-					5  0f 2  0  2  0   /* RxD0 */
-					5  0e 2  0  2  0   /* RxD1 */
-					5  0d 2  0  2  0   /* RxD2 */
-					5  0c 2  0  2  0   /* RxD3 */
-					5  1d 2  0  2  0   /* RxD4 */
-					5  1c 2  0  2  0   /* RxD5 */
-					5  1b 2  0  2  0   /* RxD6 */
-					5  1a 2  0  2  0   /* RxD7 */
-					5  0b 1  0  2  0   /* TX_EN */
-					5  18 1  0  2  0   /* TX_ER */
-					5  10 2  0  2  0   /* RX_DV */
-					5  1e 2  0  2  0   /* RX_ER */
-					5  11 2  0  2  0   /* RX_CLK */
-					5  13 1  0  2  0   /* GTX_CLK */
-					1  1f 2  0  3  0   /* GTX125 */
-					4  06 3  0  2  0   /* MDIO */
-					4  05 1  0  2  0>; /* MDC */
+					0x5  0xa 0x1  0x0  0x2  0x0   /* TxD0 */
+					0x5  0x9 0x1  0x0  0x2  0x0   /* TxD1 */
+					0x5  0x8 0x1  0x0  0x2  0x0   /* TxD2 */
+					0x5  0x7 0x1  0x0  0x2  0x0   /* TxD3 */
+					0x5  0x17 0x1  0x0  0x2  0x0   /* TxD4 */
+					0x5  0x16 0x1  0x0  0x2  0x0   /* TxD5 */
+					0x5  0x15 0x1  0x0  0x2  0x0   /* TxD6 */
+					0x5  0x14 0x1  0x0  0x2  0x0   /* TxD7 */
+					0x5  0xf 0x2  0x0  0x2  0x0   /* RxD0 */
+					0x5  0xe 0x2  0x0  0x2  0x0   /* RxD1 */
+					0x5  0xd 0x2  0x0  0x2  0x0   /* RxD2 */
+					0x5  0xc 0x2  0x0  0x2  0x0   /* RxD3 */
+					0x5  0x1d 0x2  0x0  0x2  0x0   /* RxD4 */
+					0x5  0x1c 0x2  0x0  0x2  0x0   /* RxD5 */
+					0x5  0x1b 0x2  0x0  0x2  0x0   /* RxD6 */
+					0x5  0x1a 0x2  0x0  0x2  0x0   /* RxD7 */
+					0x5  0xb 0x1  0x0  0x2  0x0   /* TX_EN */
+					0x5  0x18 0x1  0x0  0x2  0x0   /* TX_ER */
+					0x5  0x10 0x2  0x0  0x2  0x0   /* RX_DV */
+					0x5  0x1e 0x2  0x0  0x2  0x0   /* RX_ER */
+					0x5  0x11 0x2  0x0  0x2  0x0   /* RX_CLK */
+					0x5  0x13 0x1  0x0  0x2  0x0   /* GTX_CLK */
+					0x1  0x1f 0x2  0x0  0x3  0x0   /* GTX125 */
+					0x4  0x6 0x3  0x0  0x2  0x0   /* MDIO */
+					0x4  0x5 0x1  0x0  0x2  0x0>; /* MDC */
 			};
 		};
 	};
@@ -285,28 +282,28 @@
 		#size-cells = <1>;
 		device_type = "qe";
 		compatible = "fsl,qe";
-		ranges = <0 e0080000 00040000>;
-		reg = <e0080000 480>;
+		ranges = <0x0 0xe0080000 0x40000>;
+		reg = <0xe0080000 0x480>;
 		brg-frequency = <0>;
-		bus-frequency = <179A7B00>;
+		bus-frequency = <396000000>;
 
 		muram@10000 {
  			#address-cells = <1>;
  			#size-cells = <1>;
 			compatible = "fsl,qe-muram", "fsl,cpm-muram";
-			ranges = <0 00010000 0000c000>;
+			ranges = <0x0 0x10000 0x10000>;
 
 			data-only@0 {
 				compatible = "fsl,qe-muram-data",
 					     "fsl,cpm-muram-data";
-				reg = <0 c000>;
+				reg = <0x0 0x10000>;
 			};
 		};
 
 		spi@4c0 {
 			cell-index = <0>;
 			compatible = "fsl,spi";
-			reg = <4c0 40>;
+			reg = <0x4c0 0x40>;
 			interrupts = <2>;
 			interrupt-parent = <&qeic>;
 			mode = "cpu";
@@ -315,7 +312,7 @@
 		spi@500 {
 			cell-index = <1>;
 			compatible = "fsl,spi";
-			reg = <500 40>;
+			reg = <0x500 0x40>;
 			interrupts = <1>;
 			interrupt-parent = <&qeic>;
 			mode = "cpu";
@@ -324,11 +321,9 @@
 		enet2: ucc@2000 {
 			device_type = "network";
 			compatible = "ucc_geth";
-			model = "UCC";
 			cell-index = <1>;
-			device-id = <1>;
-			reg = <2000 200>;
-			interrupts = <20>;
+			reg = <0x2000 0x200>;
+			interrupts = <32>;
 			interrupt-parent = <&qeic>;
 			local-mac-address = [ 00 00 00 00 00 00 ];
 			rx-clock-name = "none";
@@ -341,11 +336,9 @@
 		enet3: ucc@3000 {
 			device_type = "network";
 			compatible = "ucc_geth";
-			model = "UCC";
 			cell-index = <2>;
-			device-id = <2>;
-			reg = <3000 200>;
-			interrupts = <21>;
+			reg = <0x3000 0x200>;
+			interrupts = <33>;
 			interrupt-parent = <&qeic>;
 			local-mac-address = [ 00 00 00 00 00 00 ];
 			rx-clock-name = "none";
@@ -358,7 +351,7 @@
 		mdio@2120 {
 			#address-cells = <1>;
 			#size-cells = <0>;
-			reg = <2120 18>;
+			reg = <0x2120 0x18>;
 			compatible = "fsl,ucc-mdio";
 
 			/* These are the same PHYs as on
@@ -366,25 +359,25 @@
 			qe_phy0: ethernet-phy@07 {
 				interrupt-parent = <&mpic>;
 				interrupts = <1 1>;
-				reg = <7>;
+				reg = <0x7>;
 				device_type = "ethernet-phy";
 			};
 			qe_phy1: ethernet-phy@01 {
 				interrupt-parent = <&mpic>;
 				interrupts = <2 1>;
-				reg = <1>;
+				reg = <0x1>;
 				device_type = "ethernet-phy";
 			};
 			qe_phy2: ethernet-phy@02 {
 				interrupt-parent = <&mpic>;
 				interrupts = <1 1>;
-				reg = <2>;
+				reg = <0x2>;
 				device_type = "ethernet-phy";
 			};
 			qe_phy3: ethernet-phy@03 {
 				interrupt-parent = <&mpic>;
 				interrupts = <2 1>;
-				reg = <3>;
+				reg = <0x3>;
 				device_type = "ethernet-phy";
 			};
 		};
@@ -394,9 +387,9 @@
 			compatible = "fsl,qe-ic";
 			#address-cells = <0>;
 			#interrupt-cells = <1>;
-			reg = <80 80>;
+			reg = <0x80 0x80>;
 			big-endian;
-			interrupts = <2e 2 2e 2>; //high:30 low:30
+			interrupts = <46 2 46 2>; //high:30 low:30
 			interrupt-parent = <&mpic>;
 		};
 
@@ -404,30 +397,30 @@
 
 	pci0: pci@e0008000 {
 		cell-index = <0>;
-		interrupt-map-mask = <f800 0 0 7>;
+		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 		interrupt-map = <
 			/* IDSEL 0x12 AD18 */
-			9000 0 0 1 &mpic 5 1
-			9000 0 0 2 &mpic 6 1
-			9000 0 0 3 &mpic 7 1
-			9000 0 0 4 &mpic 4 1
+			0x9000 0x0 0x0 0x1 &mpic 0x5 0x1
+			0x9000 0x0 0x0 0x2 &mpic 0x6 0x1
+			0x9000 0x0 0x0 0x3 &mpic 0x7 0x1
+			0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
 
 			/* IDSEL 0x13 AD19 */
-			9800 0 0 1 &mpic 6 1
-			9800 0 0 2 &mpic 7 1
-			9800 0 0 3 &mpic 4 1
-			9800 0 0 4 &mpic 5 1>;
+			0x9800 0x0 0x0 0x1 &mpic 0x6 0x1
+			0x9800 0x0 0x0 0x2 &mpic 0x7 0x1
+			0x9800 0x0 0x0 0x3 &mpic 0x4 0x1
+			0x9800 0x0 0x0 0x4 &mpic 0x5 0x1>;
 
 		interrupt-parent = <&mpic>;
-		interrupts = <18 2>;
-		bus-range = <0 ff>;
-		ranges = <02000000 0 80000000 80000000 0 20000000
-			  01000000 0 00000000 e2000000 0 00800000>;
-		clock-frequency = <3f940aa>;
+		interrupts = <24 2>;
+		bus-range = <0 255>;
+		ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
+			  0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
+		clock-frequency = <66666666>;
 		#interrupt-cells = <1>;
 		#size-cells = <2>;
 		#address-cells = <3>;
-		reg = <e0008000 1000>;
+		reg = <0xe0008000 0x1000>;
 		compatible = "fsl,mpc8540-pci";
 		device_type = "pci";
 	};
@@ -435,39 +428,39 @@
 	/* PCI Express */
 	pci1: pcie@e000a000 {
 		cell-index = <2>;
-		interrupt-map-mask = <f800 0 0 7>;
+		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 		interrupt-map = <
 
 			/* IDSEL 0x0 (PEX) */
-			00000 0 0 1 &mpic 0 1
-			00000 0 0 2 &mpic 1 1
-			00000 0 0 3 &mpic 2 1
-			00000 0 0 4 &mpic 3 1>;
+			00000 0x0 0x0 0x1 &mpic 0x0 0x1
+			00000 0x0 0x0 0x2 &mpic 0x1 0x1
+			00000 0x0 0x0 0x3 &mpic 0x2 0x1
+			00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
 
 		interrupt-parent = <&mpic>;
-		interrupts = <1a 2>;
-		bus-range = <0 ff>;
-		ranges = <02000000 0 a0000000 a0000000 0 10000000
-			  01000000 0 00000000 e2800000 0 00800000>;
-		clock-frequency = <1fca055>;
+		interrupts = <26 2>;
+		bus-range = <0 255>;
+		ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
+			  0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
+		clock-frequency = <33333333>;
 		#interrupt-cells = <1>;
 		#size-cells = <2>;
 		#address-cells = <3>;
-		reg = <e000a000 1000>;
+		reg = <0xe000a000 0x1000>;
 		compatible = "fsl,mpc8548-pcie";
 		device_type = "pci";
 		pcie@0 {
-			reg = <0 0 0 0 0>;
+			reg = <0x0 0x0 0x0 0x0 0x0>;
 			#size-cells = <2>;
 			#address-cells = <3>;
 			device_type = "pci";
-			ranges = <02000000 0 a0000000
-				  02000000 0 a0000000
-				  0 10000000
+			ranges = <0x2000000 0x0 0xa0000000
+				  0x2000000 0x0 0xa0000000
+				  0x0 0x10000000
 
-				  01000000 0 00000000
-				  01000000 0 00000000
-				  0 00800000>;
+				  0x1000000 0x0 0x0
+				  0x1000000 0x0 0x0
+				  0x0 0x800000>;
 		};
 	};
 };

arch/powerpc/boot/dts/mpc8572ds.dts

@@ -1,7 +1,7 @@
 /*
  * MPC8572 DS Device Tree Source
  *
- * Copyright 2007 Freescale Semiconductor Inc.
+ * Copyright 2007, 2008 Freescale Semiconductor Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -9,6 +9,7 @@
  * option) any later version.
  */
 
+/dts-v1/;
 / {
 	model = "fsl,MPC8572DS";
 	compatible = "fsl,MPC8572DS";
@@ -33,11 +34,11 @@
 
 		PowerPC,8572@0 {
 			device_type = "cpu";
-			reg = <0>;
-			d-cache-line-size = <20>;	// 32 bytes
-			i-cache-line-size = <20>;	// 32 bytes
-			d-cache-size = <8000>;		// L1, 32K
-			i-cache-size = <8000>;		// L1, 32K
+			reg = <0x0>;
+			d-cache-line-size = <32>;	// 32 bytes
+			i-cache-line-size = <32>;	// 32 bytes
+			d-cache-size = <0x8000>;		// L1, 32K
+			i-cache-size = <0x8000>;		// L1, 32K
 			timebase-frequency = <0>;
 			bus-frequency = <0>;
 			clock-frequency = <0>;
@@ -45,11 +46,11 @@
 
 		PowerPC,8572@1 {
 			device_type = "cpu";
-			reg = <1>;
-			d-cache-line-size = <20>;	// 32 bytes
-			i-cache-line-size = <20>;	// 32 bytes
-			d-cache-size = <8000>;		// L1, 32K
-			i-cache-size = <8000>;		// L1, 32K
+			reg = <0x1>;
+			d-cache-line-size = <32>;	// 32 bytes
+			i-cache-line-size = <32>;	// 32 bytes
+			d-cache-size = <0x8000>;		// L1, 32K
+			i-cache-size = <0x8000>;		// L1, 32K
 			timebase-frequency = <0>;
 			bus-frequency = <0>;
 			clock-frequency = <0>;
@@ -58,38 +59,38 @@
 
 	memory {
 		device_type = "memory";
-		reg = <00000000 00000000>;	// Filled by U-Boot
+		reg = <0x0 0x0>;	// Filled by U-Boot
 	};
 
 	soc8572@ffe00000 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		device_type = "soc";
-		ranges = <00000000 ffe00000 00100000>;
-		reg = <ffe00000 00001000>;	// CCSRBAR & soc regs, remove once parse code for immrbase fixed
+		ranges = <0x0 0xffe00000 0x100000>;
+		reg = <0xffe00000 0x1000>;	// CCSRBAR & soc regs, remove once parse code for immrbase fixed
 		bus-frequency = <0>;		// Filled out by uboot.
 
 		memory-controller@2000 {
 			compatible = "fsl,mpc8572-memory-controller";
-			reg = <2000 1000>;
+			reg = <0x2000 0x1000>;
 			interrupt-parent = <&mpic>;
-			interrupts = <12 2>;
+			interrupts = <18 2>;
 		};
 
 		memory-controller@6000 {
 			compatible = "fsl,mpc8572-memory-controller";
-			reg = <6000 1000>;
+			reg = <0x6000 0x1000>;
 			interrupt-parent = <&mpic>;
-			interrupts = <12 2>;
+			interrupts = <18 2>;
 		};
 
 		l2-cache-controller@20000 {
 			compatible = "fsl,mpc8572-l2-cache-controller";
-			reg = <20000 1000>;
-			cache-line-size = <20>;	// 32 bytes
-			cache-size = <80000>;	// L2, 512K
+			reg = <0x20000 0x1000>;
+			cache-line-size = <32>;	// 32 bytes
+			cache-size = <0x80000>;	// L2, 512K
 			interrupt-parent = <&mpic>;
-			interrupts = <10 2>;
+			interrupts = <16 2>;
 		};
 
 		i2c@3000 {
@@ -97,8 +98,8 @@
 			#size-cells = <0>;
 			cell-index = <0>;
 			compatible = "fsl-i2c";
-			reg = <3000 100>;
-			interrupts = <2b 2>;
+			reg = <0x3000 0x100>;
+			interrupts = <43 2>;
 			interrupt-parent = <&mpic>;
 			dfsrr;
 		};
@@ -108,8 +109,8 @@
 			#size-cells = <0>;
 			cell-index = <1>;
 			compatible = "fsl-i2c";
-			reg = <3100 100>;
-			interrupts = <2b 2>;
+			reg = <0x3100 0x100>;
+			interrupts = <43 2>;
 			interrupt-parent = <&mpic>;
 			dfsrr;
 		};
@@ -118,27 +119,27 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			compatible = "fsl,gianfar-mdio";
-			reg = <24520 20>;
+			reg = <0x24520 0x20>;
 
 			phy0: ethernet-phy@0 {
 				interrupt-parent = <&mpic>;
-				interrupts = <a 1>;
-				reg = <0>;
+				interrupts = <10 1>;
+				reg = <0x0>;
 			};
 			phy1: ethernet-phy@1 {
 				interrupt-parent = <&mpic>;
-				interrupts = <a 1>;
-				reg = <1>;
+				interrupts = <10 1>;
+				reg = <0x1>;
 			};
 			phy2: ethernet-phy@2 {
 				interrupt-parent = <&mpic>;
-				interrupts = <a 1>;
-				reg = <2>;
+				interrupts = <10 1>;
+				reg = <0x2>;
 			};
 			phy3: ethernet-phy@3 {
 				interrupt-parent = <&mpic>;
-				interrupts = <a 1>;
-				reg = <3>;
+				interrupts = <10 1>;
+				reg = <0x3>;
 			};
 		};
 
@@ -147,9 +148,9 @@
 			device_type = "network";
 			model = "eTSEC";
 			compatible = "gianfar";
-			reg = <24000 1000>;
+			reg = <0x24000 0x1000>;
 			local-mac-address = [ 00 00 00 00 00 00 ];
-			interrupts = <1d 2 1e 2 22 2>;
+			interrupts = <29 2 30 2 34 2>;
 			interrupt-parent = <&mpic>;
 			phy-handle = <&phy0>;
 			phy-connection-type = "rgmii-id";
@@ -160,9 +161,9 @@
 			device_type = "network";
 			model = "eTSEC";
 			compatible = "gianfar";
-			reg = <25000 1000>;
+			reg = <0x25000 0x1000>;
 			local-mac-address = [ 00 00 00 00 00 00 ];
-			interrupts = <23 2 24 2 28 2>;
+			interrupts = <35 2 36 2 40 2>;
 			interrupt-parent = <&mpic>;
 			phy-handle = <&phy1>;
 			phy-connection-type = "rgmii-id";
@@ -173,9 +174,9 @@
 			device_type = "network";
 			model = "eTSEC";
 			compatible = "gianfar";
-			reg = <26000 1000>;
+			reg = <0x26000 0x1000>;
 			local-mac-address = [ 00 00 00 00 00 00 ];
-			interrupts = <1f 2 20 2 21 2>;
+			interrupts = <31 2 32 2 33 2>;
 			interrupt-parent = <&mpic>;
 			phy-handle = <&phy2>;
 			phy-connection-type = "rgmii-id";
@@ -186,9 +187,9 @@
 			device_type = "network";
 			model = "eTSEC";
 			compatible = "gianfar";
-			reg = <27000 1000>;
+			reg = <0x27000 0x1000>;
 			local-mac-address = [ 00 00 00 00 00 00 ];
-			interrupts = <25 2 26 2 27 2>;
+			interrupts = <37 2 38 2 39 2>;
 			interrupt-parent = <&mpic>;
 			phy-handle = <&phy3>;
 			phy-connection-type = "rgmii-id";
@@ -198,9 +199,9 @@
 			cell-index = <0>;
 			device_type = "serial";
 			compatible = "ns16550";
-			reg = <4500 100>;
+			reg = <0x4500 0x100>;
 			clock-frequency = <0>;
-			interrupts = <2a 2>;
+			interrupts = <42 2>;
 			interrupt-parent = <&mpic>;
 		};
 
@@ -208,15 +209,15 @@
 			cell-index = <1>;
 			device_type = "serial";
 			compatible = "ns16550";
-			reg = <4600 100>;
+			reg = <0x4600 0x100>;
 			clock-frequency = <0>;
-			interrupts = <2a 2>;
+			interrupts = <42 2>;
 			interrupt-parent = <&mpic>;
 		};
 
 		global-utilities@e0000 {	//global utilities block
 			compatible = "fsl,mpc8572-guts";
-			reg = <e0000 1000>;
+			reg = <0xe0000 0x1000>;
 			fsl,has-rstcr;
 		};
 
@@ -225,7 +226,7 @@
 			interrupt-controller;
 			#address-cells = <0>;
 			#interrupt-cells = <2>;
-			reg = <40000 40000>;
+			reg = <0x40000 0x40000>;
 			compatible = "chrp,open-pic";
 			device_type = "open-pic";
 			big-endian;
@@ -239,167 +240,167 @@
 		#interrupt-cells = <1>;
 		#size-cells = <2>;
 		#address-cells = <3>;
-		reg = <ffe08000 1000>;
-		bus-range = <0 ff>;
-		ranges = <02000000 0 80000000 80000000 0 20000000
-			  01000000 0 00000000 ffc00000 0 00010000>;
-		clock-frequency = <1fca055>;
+		reg = <0xffe08000 0x1000>;
+		bus-range = <0 255>;
+		ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
+			  0x1000000 0x0 0x0 0xffc00000 0x0 0x10000>;
+		clock-frequency = <33333333>;
 		interrupt-parent = <&mpic>;
-		interrupts = <18 2>;
-		interrupt-map-mask = <ff00 0 0 7>;
+		interrupts = <24 2>;
+		interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
 		interrupt-map = <
 			/* IDSEL 0x11 func 0 - PCI slot 1 */
-			8800 0 0 1 &mpic 2 1
-			8800 0 0 2 &mpic 3 1
-			8800 0 0 3 &mpic 4 1
-			8800 0 0 4 &mpic 1 1
+			0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
+			0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
+			0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
+			0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
 
 			/* IDSEL 0x11 func 1 - PCI slot 1 */
-			8900 0 0 1 &mpic 2 1
-			8900 0 0 2 &mpic 3 1
-			8900 0 0 3 &mpic 4 1
-			8900 0 0 4 &mpic 1 1
+			0x8900 0x0 0x0 0x1 &mpic 0x2 0x1
+			0x8900 0x0 0x0 0x2 &mpic 0x3 0x1
+			0x8900 0x0 0x0 0x3 &mpic 0x4 0x1
+			0x8900 0x0 0x0 0x4 &mpic 0x1 0x1
 
 			/* IDSEL 0x11 func 2 - PCI slot 1 */
-			8a00 0 0 1 &mpic 2 1
-			8a00 0 0 2 &mpic 3 1
-			8a00 0 0 3 &mpic 4 1
-			8a00 0 0 4 &mpic 1 1
+			0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1
+			0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1
+			0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1
+			0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1
 
 			/* IDSEL 0x11 func 3 - PCI slot 1 */
-			8b00 0 0 1 &mpic 2 1
-			8b00 0 0 2 &mpic 3 1
-			8b00 0 0 3 &mpic 4 1
-			8b00 0 0 4 &mpic 1 1
+			0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1
+			0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1
+			0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1
+			0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1
 
 			/* IDSEL 0x11 func 4 - PCI slot 1 */
-			8c00 0 0 1 &mpic 2 1
-			8c00 0 0 2 &mpic 3 1
-			8c00 0 0 3 &mpic 4 1
-			8c00 0 0 4 &mpic 1 1
+			0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1
+			0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1
+			0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1
+			0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1
 
 			/* IDSEL 0x11 func 5 - PCI slot 1 */
-			8d00 0 0 1 &mpic 2 1
-			8d00 0 0 2 &mpic 3 1
-			8d00 0 0 3 &mpic 4 1
-			8d00 0 0 4 &mpic 1 1
+			0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1
+			0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1
+			0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1
+			0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1
 
 			/* IDSEL 0x11 func 6 - PCI slot 1 */
-			8e00 0 0 1 &mpic 2 1
-			8e00 0 0 2 &mpic 3 1
-			8e00 0 0 3 &mpic 4 1
-			8e00 0 0 4 &mpic 1 1
+			0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1
+			0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1
+			0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1
+			0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1
 
 			/* IDSEL 0x11 func 7 - PCI slot 1 */
-			8f00 0 0 1 &mpic 2 1
-			8f00 0 0 2 &mpic 3 1
-			8f00 0 0 3 &mpic 4 1
-			8f00 0 0 4 &mpic 1 1
+			0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1
+			0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1
+			0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1
+			0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1
 
 			/* IDSEL 0x12 func 0 - PCI slot 2 */
-			9000 0 0 1 &mpic 3 1
-			9000 0 0 2 &mpic 4 1
-			9000 0 0 3 &mpic 1 1
-			9000 0 0 4 &mpic 2 1
+			0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
+			0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
+			0x9000 0x0 0x0 0x3 &mpic 0x1 0x1
+			0x9000 0x0 0x0 0x4 &mpic 0x2 0x1
 
 			/* IDSEL 0x12 func 1 - PCI slot 2 */
-			9100 0 0 1 &mpic 3 1
-			9100 0 0 2 &mpic 4 1
-			9100 0 0 3 &mpic 1 1
-			9100 0 0 4 &mpic 2 1
+			0x9100 0x0 0x0 0x1 &mpic 0x3 0x1
+			0x9100 0x0 0x0 0x2 &mpic 0x4 0x1
+			0x9100 0x0 0x0 0x3 &mpic 0x1 0x1
+			0x9100 0x0 0x0 0x4 &mpic 0x2 0x1
 
 			/* IDSEL 0x12 func 2 - PCI slot 2 */
-			9200 0 0 1 &mpic 3 1
-			9200 0 0 2 &mpic 4 1
-			9200 0 0 3 &mpic 1 1
-			9200 0 0 4 &mpic 2 1
+			0x9200 0x0 0x0 0x1 &mpic 0x3 0x1
+			0x9200 0x0 0x0 0x2 &mpic 0x4 0x1
+			0x9200 0x0 0x0 0x3 &mpic 0x1 0x1
+			0x9200 0x0 0x0 0x4 &mpic 0x2 0x1
 
 			/* IDSEL 0x12 func 3 - PCI slot 2 */
-			9300 0 0 1 &mpic 3 1
-			9300 0 0 2 &mpic 4 1
-			9300 0 0 3 &mpic 1 1
-			9300 0 0 4 &mpic 2 1
+			0x9300 0x0 0x0 0x1 &mpic 0x3 0x1
+			0x9300 0x0 0x0 0x2 &mpic 0x4 0x1
+			0x9300 0x0 0x0 0x3 &mpic 0x1 0x1
+			0x9300 0x0 0x0 0x4 &mpic 0x2 0x1
 
 			/* IDSEL 0x12 func 4 - PCI slot 2 */
-			9400 0 0 1 &mpic 3 1
-			9400 0 0 2 &mpic 4 1
-			9400 0 0 3 &mpic 1 1
-			9400 0 0 4 &mpic 2 1
+			0x9400 0x0 0x0 0x1 &mpic 0x3 0x1
+			0x9400 0x0 0x0 0x2 &mpic 0x4 0x1
+			0x9400 0x0 0x0 0x3 &mpic 0x1 0x1
+			0x9400 0x0 0x0 0x4 &mpic 0x2 0x1
 
 			/* IDSEL 0x12 func 5 - PCI slot 2 */
-			9500 0 0 1 &mpic 3 1
-			9500 0 0 2 &mpic 4 1
-			9500 0 0 3 &mpic 1 1
-			9500 0 0 4 &mpic 2 1
+			0x9500 0x0 0x0 0x1 &mpic 0x3 0x1
+			0x9500 0x0 0x0 0x2 &mpic 0x4 0x1
+			0x9500 0x0 0x0 0x3 &mpic 0x1 0x1
+			0x9500 0x0 0x0 0x4 &mpic 0x2 0x1
 
 			/* IDSEL 0x12 func 6 - PCI slot 2 */
-			9600 0 0 1 &mpic 3 1
-			9600 0 0 2 &mpic 4 1
-			9600 0 0 3 &mpic 1 1
-			9600 0 0 4 &mpic 2 1
+			0x9600 0x0 0x0 0x1 &mpic 0x3 0x1
+			0x9600 0x0 0x0 0x2 &mpic 0x4 0x1
+			0x9600 0x0 0x0 0x3 &mpic 0x1 0x1
+			0x9600 0x0 0x0 0x4 &mpic 0x2 0x1
 
 			/* IDSEL 0x12 func 7 - PCI slot 2 */
-			9700 0 0 1 &mpic 3 1
-			9700 0 0 2 &mpic 4 1
-			9700 0 0 3 &mpic 1 1
-			9700 0 0 4 &mpic 2 1
+			0x9700 0x0 0x0 0x1 &mpic 0x3 0x1
+			0x9700 0x0 0x0 0x2 &mpic 0x4 0x1
+			0x9700 0x0 0x0 0x3 &mpic 0x1 0x1
+			0x9700 0x0 0x0 0x4 &mpic 0x2 0x1
 
 			// IDSEL 0x1c  USB
-			e000 0 0 1 &i8259 c 2
-			e100 0 0 2 &i8259 9 2
-			e200 0 0 3 &i8259 a 2
-			e300 0 0 4 &i8259 b 2
+			0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
+			0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
+			0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
+			0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
 
 			// IDSEL 0x1d  Audio
-			e800 0 0 1 &i8259 6 2
+			0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
 
 			// IDSEL 0x1e Legacy
-			f000 0 0 1 &i8259 7 2
-			f100 0 0 1 &i8259 7 2
+			0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
+			0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
 
 			// IDSEL 0x1f IDE/SATA
-			f800 0 0 1 &i8259 e 2
-			f900 0 0 1 &i8259 5 2
+			0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
+			0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
 
 			>;
 
 		pcie@0 {
-			reg = <0 0 0 0 0>;
+			reg = <0x0 0x0 0x0 0x0 0x0>;
 			#size-cells = <2>;
 			#address-cells = <3>;
 			device_type = "pci";
-			ranges = <02000000 0 80000000
-				  02000000 0 80000000
-				  0 20000000
+			ranges = <0x2000000 0x0 0x80000000
+				  0x2000000 0x0 0x80000000
+				  0x0 0x20000000
 
-				  01000000 0 00000000
-				  01000000 0 00000000
-				  0 00100000>;
+				  0x1000000 0x0 0x0
+				  0x1000000 0x0 0x0
+				  0x0 0x100000>;
 			uli1575@0 {
-				reg = <0 0 0 0 0>;
+				reg = <0x0 0x0 0x0 0x0 0x0>;
 				#size-cells = <2>;
 				#address-cells = <3>;
-				ranges = <02000000 0 80000000
-					  02000000 0 80000000
-					  0 20000000
+				ranges = <0x2000000 0x0 0x80000000
+					  0x2000000 0x0 0x80000000
+					  0x0 0x20000000
 
-					  01000000 0 00000000
-					  01000000 0 00000000
-					  0 00100000>;
+					  0x1000000 0x0 0x0
+					  0x1000000 0x0 0x0
+					  0x0 0x100000>;
 				isa@1e {
 					device_type = "isa";
 					#interrupt-cells = <2>;
 					#size-cells = <1>;
 					#address-cells = <2>;
-					reg = <f000 0 0 0 0>;
-					ranges = <1 0 01000000 0 0
-						  00001000>;
+					reg = <0xf000 0x0 0x0 0x0 0x0>;
+					ranges = <0x1 0x0 0x1000000 0x0 0x0
+						  0x1000>;
 					interrupt-parent = <&i8259>;
 
 					i8259: interrupt-controller@20 {
-						reg = <1 20 2
-						       1 a0 2
-						       1 4d0 2>;
+						reg = <0x1 0x20 0x2
+						       0x1 0xa0 0x2
+						       0x1 0x4d0 0x2>;
 						interrupt-controller;
 						device_type = "interrupt-controller";
 						#address-cells = <0>;
@@ -412,29 +413,29 @@
 					i8042@60 {
 						#size-cells = <0>;
 						#address-cells = <1>;
-						reg = <1 60 1 1 64 1>;
-						interrupts = <1 3 c 3>;
+						reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
+						interrupts = <1 3 12 3>;
 						interrupt-parent =
 							<&i8259>;
 
 						keyboard@0 {
-							reg = <0>;
+							reg = <0x0>;
 							compatible = "pnpPNP,303";
 						};
 
 						mouse@1 {
-							reg = <1>;
+							reg = <0x1>;
 							compatible = "pnpPNP,f03";
 						};
 					};
 
 					rtc@70 {
 						compatible = "pnpPNP,b00";
-						reg = <1 70 2>;
+						reg = <0x1 0x70 0x2>;
 					};
 
 					gpio@400 {
-						reg = <1 400 80>;
+						reg = <0x1 0x400 0x80>;
 					};
 				};
 			};
@@ -449,33 +450,33 @@
 		#interrupt-cells = <1>;
 		#size-cells = <2>;
 		#address-cells = <3>;
-		reg = <ffe09000 1000>;
-		bus-range = <0 ff>;
-		ranges = <02000000 0 a0000000 a0000000 0 20000000
-			  01000000 0 00000000 ffc10000 0 00010000>;
-		clock-frequency = <1fca055>;
+		reg = <0xffe09000 0x1000>;
+		bus-range = <0 255>;
+		ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
+			  0x1000000 0x0 0x0 0xffc10000 0x0 0x10000>;
+		clock-frequency = <33333333>;
 		interrupt-parent = <&mpic>;
-		interrupts = <1a 2>;
-		interrupt-map-mask = <f800 0 0 7>;
+		interrupts = <26 2>;
+		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 		interrupt-map = <
 			/* IDSEL 0x0 */
-			0000 0 0 1 &mpic 4 1
-			0000 0 0 2 &mpic 5 1
-			0000 0 0 3 &mpic 6 1
-			0000 0 0 4 &mpic 7 1
+			0000 0x0 0x0 0x1 &mpic 0x4 0x1
+			0000 0x0 0x0 0x2 &mpic 0x5 0x1
+			0000 0x0 0x0 0x3 &mpic 0x6 0x1
+			0000 0x0 0x0 0x4 &mpic 0x7 0x1
 			>;
 		pcie@0 {
-			reg = <0 0 0 0 0>;
+			reg = <0x0 0x0 0x0 0x0 0x0>;
 			#size-cells = <2>;
 			#address-cells = <3>;
 			device_type = "pci";
-			ranges = <02000000 0 a0000000
-				  02000000 0 a0000000
-				  0 20000000
+			ranges = <0x2000000 0x0 0xa0000000
+				  0x2000000 0x0 0xa0000000
+				  0x0 0x20000000
 
-				  01000000 0 00000000
-				  01000000 0 00000000
-				  0 00100000>;
+				  0x1000000 0x0 0x0
+				  0x1000000 0x0 0x0
+				  0x0 0x100000>;
 		};
 	};
 
@@ -486,33 +487,33 @@
 		#interrupt-cells = <1>;
 		#size-cells = <2>;
 		#address-cells = <3>;
-		reg = <ffe0a000 1000>;
-		bus-range = <0 ff>;
-		ranges = <02000000 0 c0000000 c0000000 0 20000000
-			  01000000 0 00000000 ffc20000 0 00010000>;
-		clock-frequency = <1fca055>;
+		reg = <0xffe0a000 0x1000>;
+		bus-range = <0 255>;
+		ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
+			  0x1000000 0x0 0x0 0xffc20000 0x0 0x10000>;
+		clock-frequency = <33333333>;
 		interrupt-parent = <&mpic>;
-		interrupts = <1b 2>;
-		interrupt-map-mask = <f800 0 0 7>;
+		interrupts = <27 2>;
+		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 		interrupt-map = <
 			/* IDSEL 0x0 */
-			0000 0 0 1 &mpic 0 1
-			0000 0 0 2 &mpic 1 1
-			0000 0 0 3 &mpic 2 1
-			0000 0 0 4 &mpic 3 1
+			0000 0x0 0x0 0x1 &mpic 0x0 0x1
+			0000 0x0 0x0 0x2 &mpic 0x1 0x1
+			0000 0x0 0x0 0x3 &mpic 0x2 0x1
+			0000 0x0 0x0 0x4 &mpic 0x3 0x1
 			>;
 		pcie@0 {
-			reg = <0 0 0 0 0>;
+			reg = <0x0 0x0 0x0 0x0 0x0>;
 			#size-cells = <2>;
 			#address-cells = <3>;
 			device_type = "pci";
-			ranges = <02000000 0 c0000000
-				  02000000 0 c0000000
-				  0 20000000
+			ranges = <0x2000000 0x0 0xc0000000
+				  0x2000000 0x0 0xc0000000
+				  0x0 0x20000000
 
-				  01000000 0 00000000
-				  01000000 0 00000000
-				  0 00100000>;
+				  0x1000000 0x0 0x0
+				  0x1000000 0x0 0x0
+				  0x0 0x100000>;
 		};
 	};
 };

arch/powerpc/boot/dts/mpc8641_hpcn.dts

@@ -13,7 +13,7 @@
 
 / {
 	model = "MPC8641HPCN";
-	compatible = "mpc86xx";
+	compatible = "fsl,mpc8641hpcn";
 	#address-cells = <1>;
 	#size-cells = <1>;
 

arch/powerpc/boot/dts/mpc866ads.dts

@@ -2,6 +2,7 @@
  * MPC866 ADS Device Tree Source
  *
  * Copyright 2006 MontaVista Software, Inc.
+ * Copyright 2008 Freescale Semiconductor, Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -9,6 +10,7 @@
  * option) any later version.
  */
 
+/dts-v1/;
 
 / {
 	model = "MPC866ADS";
@@ -22,37 +24,37 @@
 
 		PowerPC,866@0 {
 			device_type = "cpu";
-			reg = <0>;
-			d-cache-line-size = <10>;	// 16 bytes
-			i-cache-line-size = <10>;	// 16 bytes
-			d-cache-size = <2000>;		// L1, 8K
-			i-cache-size = <4000>;		// L1, 16K
+			reg = <0x0>;
+			d-cache-line-size = <16>;	// 16 bytes
+			i-cache-line-size = <16>;	// 16 bytes
+			d-cache-size = <0x2000>;		// L1, 8K
+			i-cache-size = <0x4000>;		// L1, 16K
 			timebase-frequency = <0>;
 			bus-frequency = <0>;
 			clock-frequency = <0>;
-			interrupts = <f 2>;	// decrementer interrupt
+			interrupts = <15 2>;	// decrementer interrupt
 			interrupt-parent = <&PIC>;
 		};
 	};
 
 	memory {
 		device_type = "memory";
-		reg = <00000000 800000>;
+		reg = <0x0 0x800000>;
 	};
 
 	localbus@ff000100 {
 		compatible = "fsl,mpc866-localbus", "fsl,pq1-localbus";
 		#address-cells = <2>;
 		#size-cells = <1>;
-		reg = <ff000100 40>;
+		reg = <0xff000100 0x40>;
 
 		ranges = <
-			1 0 ff080000 00008000
-			5 0 ff0a0000 00008000
+			0x1 0x0 0xff080000 0x8000
+			0x5 0x0 0xff0a0000 0x8000
 		>;
 
 		board-control@1,0 {
-			reg = <1 0 20 5 300 4>;
+			reg = <0x1 0x0 0x20 0x5 0x300 0x4>;
 			compatible = "fsl,mpc866ads-bcsr";
 		};
 	};
@@ -61,17 +63,17 @@
 		#address-cells = <1>;
 		#size-cells = <1>;
 		device_type = "soc";
-		ranges = <0 ff000000 00100000>;
-		reg = <ff000000 00000200>;
+		ranges = <0x0 0xff000000 0x100000>;
+		reg = <0xff000000 0x200>;
 		bus-frequency = <0>;
 
 		mdio@e00 {
 			compatible = "fsl,mpc866-fec-mdio", "fsl,pq1-fec-mdio";
-			reg = <e00 188>;
+			reg = <0xe00 0x188>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			PHY: ethernet-phy@f {
-				reg = <f>;
+				reg = <0xf>;
 				device_type = "ethernet-phy";
 			};
 		};
@@ -80,7 +82,7 @@
 			device_type = "network";
 			compatible = "fsl,mpc866-fec-enet",
 			             "fsl,pq1-fec-enet";
-			reg = <e00 188>;
+			reg = <0xe00 0x188>;
 			local-mac-address = [ 00 00 00 00 00 00 ];
 			interrupts = <3 1>;
 			interrupt-parent = <&PIC>;
@@ -91,7 +93,7 @@
 		PIC: pic@0 {
 			interrupt-controller;
 			#interrupt-cells = <2>;
-			reg = <0 24>;
+			reg = <0x0 0x24>;
 			compatible = "fsl,mpc866-pic", "fsl,pq1-pic";
 		};
 
@@ -100,7 +102,7 @@
 			#size-cells = <1>;
 			compatible = "fsl,mpc866-cpm", "fsl,cpm1";
 			ranges;
-			reg = <9c0 40>;
+			reg = <0x9c0 0x40>;
 			brg-frequency = <0>;
 			interrupts = <0 2>;	// cpm error interrupt
 			interrupt-parent = <&CPM_PIC>;
@@ -108,11 +110,11 @@
 			muram@2000 {
 				#address-cells = <1>;
 				#size-cells = <1>;
-				ranges = <0 2000 2000>;
+				ranges = <0x0 0x2000 0x2000>;
 
 				data@0 {
 					compatible = "fsl,cpm-muram-data";
-					reg = <0 1c00>;
+					reg = <0x0 0x1c00>;
 				};
 			};
 
@@ -120,7 +122,7 @@
 				compatible = "fsl,mpc866-brg",
 					     "fsl,cpm1-brg",
 					     "fsl,cpm-brg";
-				reg = <9f0 10>;
+				reg = <0x9f0 0x10>;
 				clock-frequency = <0>;
 			};
 
@@ -130,7 +132,7 @@
 				#interrupt-cells = <1>;
 				interrupts = <5 2 0 2>;
 				interrupt-parent = <&PIC>;
-				reg = <930 20>;
+				reg = <0x930 0x20>;
 				compatible = "fsl,mpc866-cpm-pic",
 				             "fsl,cpm1-pic";
 			};
@@ -140,31 +142,31 @@
 				device_type = "serial";
 				compatible = "fsl,mpc866-smc-uart",
 				             "fsl,cpm1-smc-uart";
-				reg = <a80 10 3e80 40>;
+				reg = <0xa80 0x10 0x3e80 0x40>;
 				interrupts = <4>;
 				interrupt-parent = <&CPM_PIC>;
 				fsl,cpm-brg = <1>;
-				fsl,cpm-command = <0090>;
+				fsl,cpm-command = <0x90>;
 			};
 
 			serial@a90 {
 				device_type = "serial";
 				compatible = "fsl,mpc866-smc-uart",
 				             "fsl,cpm1-smc-uart";
-				reg = <a90 10 3f80 40>;
+				reg = <0xa90 0x10 0x3f80 0x40>;
 				interrupts = <3>;
 				interrupt-parent = <&CPM_PIC>;
 				fsl,cpm-brg = <2>;
-				fsl,cpm-command = <00d0>;
+				fsl,cpm-command = <0xd0>;
 			};
 
 			ethernet@a00 {
 				device_type = "network";
 				compatible = "fsl,mpc866-scc-enet",
 				             "fsl,cpm1-scc-enet";
-				reg = <a00 18 3c00 100>;
+				reg = <0xa00 0x18 0x3c00 0x100>;
 				local-mac-address = [ 00 00 00 00 00 00 ];
-				interrupts = <1e>;
+				interrupts = <30>;
 				interrupt-parent = <&CPM_PIC>;
 				fsl,cpm-command = <0000>;
 				linux,network-index = <1>;

arch/powerpc/boot/dts/mpc885ads.dts

@@ -2,7 +2,7 @@
  * MPC885 ADS Device Tree Source
  *
  * Copyright 2006 MontaVista Software, Inc.
- * Copyright 2007 Freescale Semiconductor, Inc.
+ * Copyright 2007,2008 Freescale Semiconductor, Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -10,6 +10,7 @@
  * option) any later version.
  */
 
+/dts-v1/;
 
 / {
 	model = "MPC885ADS";
@@ -23,45 +24,45 @@
 
 		PowerPC,885@0 {
 			device_type = "cpu";
-			reg = <0>;
-			d-cache-line-size = <d#16>;
-			i-cache-line-size = <d#16>;
-			d-cache-size = <d#8192>;
-			i-cache-size = <d#8192>;
+			reg = <0x0>;
+			d-cache-line-size = <16>;
+			i-cache-line-size = <16>;
+			d-cache-size = <8192>;
+			i-cache-size = <8192>;
 			timebase-frequency = <0>;
 			bus-frequency = <0>;
 			clock-frequency = <0>;
-			interrupts = <f 2>;	// decrementer interrupt
+			interrupts = <15 2>;	// decrementer interrupt
 			interrupt-parent = <&PIC>;
 		};
 	};
 
 	memory {
 		device_type = "memory";
-		reg = <0 0>;
+		reg = <0x0 0x0>;
 	};
 
 	localbus@ff000100 {
 		compatible = "fsl,mpc885-localbus", "fsl,pq1-localbus";
 		#address-cells = <2>;
 		#size-cells = <1>;
-		reg = <ff000100 40>;
+		reg = <0xff000100 0x40>;
 
 		ranges = <
-			0 0 fe000000 00800000
-			1 0 ff080000 00008000
-			5 0 ff0a0000 00008000
+			0x0 0x0 0xfe000000 0x800000
+			0x1 0x0 0xff080000 0x8000
+			0x5 0x0 0xff0a0000 0x8000
 		>;
 
 		flash@0,0 {
 			compatible = "jedec-flash";
-			reg = <0 0 800000>;
+			reg = <0x0 0x0 0x800000>;
 			bank-width = <4>;
 			device-width = <1>;
 		};
 
 		board-control@1,0 {
-			reg = <1 0 20 5 300 4>;
+			reg = <0x1 0x0 0x20 0x5 0x300 0x4>;
 			compatible = "fsl,mpc885ads-bcsr";
 		};
 	};
@@ -71,30 +72,30 @@
 		#address-cells = <1>;
 		#size-cells = <1>;
 		device_type = "soc";
-		ranges = <0 ff000000 00004000>;
+		ranges = <0x0 0xff000000 0x4000>;
 		bus-frequency = <0>;
 
 		// Temporary -- will go away once kernel uses ranges for get_immrbase().
-		reg = <ff000000 4000>;
+		reg = <0xff000000 0x4000>;
 
 		mdio@e00 {
 			compatible = "fsl,mpc885-fec-mdio", "fsl,pq1-fec-mdio";
-			reg = <e00 188>;
+			reg = <0xe00 0x188>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 
 			PHY0: ethernet-phy@0 {
-				reg = <0>;
+				reg = <0x0>;
 				device_type = "ethernet-phy";
 			};
 
 			PHY1: ethernet-phy@1 {
-				reg = <1>;
+				reg = <0x1>;
 				device_type = "ethernet-phy";
 			};
 
 			PHY2: ethernet-phy@2 {
-				reg = <2>;
+				reg = <0x2>;
 				device_type = "ethernet-phy";
 			};
 		};
@@ -103,7 +104,7 @@
 			device_type = "network";
 			compatible = "fsl,mpc885-fec-enet",
 			             "fsl,pq1-fec-enet";
-			reg = <e00 188>;
+			reg = <0xe00 0x188>;
 			local-mac-address = [ 00 00 00 00 00 00 ];
 			interrupts = <3 1>;
 			interrupt-parent = <&PIC>;
@@ -115,7 +116,7 @@
 			device_type = "network";
 			compatible = "fsl,mpc885-fec-enet",
 			             "fsl,pq1-fec-enet";
-			reg = <1e00 188>;
+			reg = <0x1e00 0x188>;
 			local-mac-address = [ 00 00 00 00 00 00 ];
 			interrupts = <7 1>;
 			interrupt-parent = <&PIC>;
@@ -126,7 +127,7 @@
 		PIC: interrupt-controller@0 {
 			interrupt-controller;
 			#interrupt-cells = <2>;
-			reg = <0 24>;
+			reg = <0x0 0x24>;
 			compatible = "fsl,mpc885-pic", "fsl,pq1-pic";
 		};
 
@@ -136,29 +137,29 @@
 			#size-cells = <2>;
 			compatible = "fsl,pq-pcmcia";
 			device_type = "pcmcia";
-			reg = <80 80>;
+			reg = <0x80 0x80>;
 			interrupt-parent = <&PIC>;
-			interrupts = <d 1>;
+			interrupts = <13 1>;
 		};
 
 		cpm@9c0 {
 			#address-cells = <1>;
 			#size-cells = <1>;
 			compatible = "fsl,mpc885-cpm", "fsl,cpm1";
-			command-proc = <9c0>;
+			command-proc = <0x9c0>;
 			interrupts = <0>;	// cpm error interrupt
 			interrupt-parent = <&CPM_PIC>;
-			reg = <9c0 40>;
+			reg = <0x9c0 0x40>;
 			ranges;
 
 			muram@2000 {
 				#address-cells = <1>;
 				#size-cells = <1>;
-				ranges = <0 2000 2000>;
+				ranges = <0x0 0x2000 0x2000>;
 
 				data@0 {
 					compatible = "fsl,cpm-muram-data";
-					reg = <0 1c00>;
+					reg = <0x0 0x1c00>;
 				};
 			};
 
@@ -167,7 +168,7 @@
 				             "fsl,cpm1-brg",
 				             "fsl,cpm-brg";
 				clock-frequency = <0>;
-				reg = <9f0 10>;
+				reg = <0x9f0 0x10>;
 			};
 
 			CPM_PIC: interrupt-controller@930 {
@@ -175,7 +176,7 @@
 				#interrupt-cells = <1>;
 				interrupts = <5 2 0 2>;
 				interrupt-parent = <&PIC>;
-				reg = <930 20>;
+				reg = <0x930 0x20>;
 				compatible = "fsl,mpc885-cpm-pic",
 				             "fsl,cpm1-pic";
 			};
@@ -184,34 +185,34 @@
 				device_type = "serial";
 				compatible = "fsl,mpc885-smc-uart",
 				             "fsl,cpm1-smc-uart";
-				reg = <a80 10 3e80 40>;
+				reg = <0xa80 0x10 0x3e80 0x40>;
 				interrupts = <4>;
 				interrupt-parent = <&CPM_PIC>;
 				fsl,cpm-brg = <1>;
-				fsl,cpm-command = <0090>;
+				fsl,cpm-command = <0x90>;
 			};
 
 			serial@a90 {
 				device_type = "serial";
 				compatible = "fsl,mpc885-smc-uart",
 				             "fsl,cpm1-smc-uart";
-				reg = <a90 10 3f80 40>;
+				reg = <0xa90 0x10 0x3f80 0x40>;
 				interrupts = <3>;
 				interrupt-parent = <&CPM_PIC>;
 				fsl,cpm-brg = <2>;
-				fsl,cpm-command = <00d0>;
+				fsl,cpm-command = <0xd0>;
 			};
 
 			ethernet@a40 {
 				device_type = "network";
 				compatible = "fsl,mpc885-scc-enet",
 				             "fsl,cpm1-scc-enet";
-				reg = <a40 18 3e00 100>;
+				reg = <0xa40 0x18 0x3e00 0x100>;
 				local-mac-address = [ 00 00 00 00 00 00 ];
-				interrupts = <1c>;
+				interrupts = <28>;
 				interrupt-parent = <&CPM_PIC>;
 				phy-handle = <&PHY2>;
-				fsl,cpm-command = <0080>;
+				fsl,cpm-command = <0x80>;
 				linux,network-index = <2>;
 			};
 		};

arch/powerpc/boot/dts/pq2fads.dts

@@ -1,7 +1,7 @@
 /*
  * Device Tree for the PQ2FADS-ZU board with an MPC8280 chip.
  *
- * Copyright 2007 Freescale Semiconductor Inc.
+ * Copyright 2007,2008 Freescale Semiconductor Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -9,6 +9,8 @@
  * option) any later version.
  */
 
+/dts-v1/;
+
 / {
 	model = "pq2fads";
 	compatible = "fsl,pq2fads";
@@ -21,11 +23,11 @@
 
 		cpu@0 {
 			device_type = "cpu";
-			reg = <0>;
-			d-cache-line-size = <d#32>;
-			i-cache-line-size = <d#32>;
-			d-cache-size = <d#16384>;
-			i-cache-size = <d#16384>;
+			reg = <0x0>;
+			d-cache-line-size = <32>;
+			i-cache-line-size = <32>;
+			d-cache-size = <16384>;
+			i-cache-size = <16384>;
 			timebase-frequency = <0>;
 			clock-frequency = <0>;
 		};
@@ -33,7 +35,7 @@
 
 	memory {
 		device_type = "memory";
-		reg = <0 0>;
+		reg = <0x0 0x0>;
 	};
 
 	localbus@f0010100 {
@@ -41,67 +43,67 @@
 		             "fsl,pq2-localbus";
 		#address-cells = <2>;
 		#size-cells = <1>;
-		reg = <f0010100 60>;
+		reg = <0xf0010100 0x60>;
 
-		ranges = <0 0 fe000000 00800000
-		          1 0 f4500000 00008000
-		          8 0 f8200000 00008000>;
+		ranges = <0x0 0x0 0xfe000000 0x800000
+		          0x1 0x0 0xf4500000 0x8000
+		          0x8 0x0 0xf8200000 0x8000>;
 
 		flash@0,0 {
 			compatible = "jedec-flash";
-			reg = <0 0 800000>;
+			reg = <0x0 0x0 0x800000>;
 			bank-width = <4>;
 			device-width = <1>;
 		};
 
 		bcsr@1,0 {
-			reg = <1 0 20>;
+			reg = <0x1 0x0 0x20>;
 			compatible = "fsl,pq2fads-bcsr";
 		};
 
 		PCI_PIC: pic@8,0 {
 			#interrupt-cells = <1>;
 			interrupt-controller;
-			reg = <8 0 8>;
+			reg = <0x8 0x0 0x8>;
 			compatible = "fsl,pq2ads-pci-pic";
 			interrupt-parent = <&PIC>;
-			interrupts = <18 8>;
+			interrupts = <24 8>;
 		};
 	};
 
 	pci@f0010800 {
 		device_type = "pci";
-		reg = <f0010800 10c f00101ac 8 f00101c4 8>;
+		reg = <0xf0010800 0x10c 0xf00101ac 0x8 0xf00101c4 0x8>;
 		compatible = "fsl,mpc8280-pci", "fsl,pq2-pci";
 		#interrupt-cells = <1>;
 		#size-cells = <2>;
 		#address-cells = <3>;
-		clock-frequency = <d#66000000>;
-		interrupt-map-mask = <f800 0 0 7>;
+		clock-frequency = <66000000>;
+		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 		interrupt-map = <
 		                /* IDSEL 0x16 */
-		                 b000 0 0 1 &PCI_PIC 0
-		                 b000 0 0 2 &PCI_PIC 1
-		                 b000 0 0 3 &PCI_PIC 2
-		                 b000 0 0 4 &PCI_PIC 3
+		                 0xb000 0x0 0x0 0x1 &PCI_PIC 0
+		                 0xb000 0x0 0x0 0x2 &PCI_PIC 1
+		                 0xb000 0x0 0x0 0x3 &PCI_PIC 2
+		                 0xb000 0x0 0x0 0x4 &PCI_PIC 3
 
 		                /* IDSEL 0x17 */
-		                 b800 0 0 1 &PCI_PIC 4
-		                 b800 0 0 2 &PCI_PIC 5
-		                 b800 0 0 3 &PCI_PIC 6
-		                 b800 0 0 4 &PCI_PIC 7
+		                 0xb800 0x0 0x0 0x1 &PCI_PIC 4
+		                 0xb800 0x0 0x0 0x2 &PCI_PIC 5
+		                 0xb800 0x0 0x0 0x3 &PCI_PIC 6
+		                 0xb800 0x0 0x0 0x4 &PCI_PIC 7
 
 		                /* IDSEL 0x18 */
-		                 c000 0 0 1 &PCI_PIC 8
-		                 c000 0 0 2 &PCI_PIC 9
-		                 c000 0 0 3 &PCI_PIC a
-		                 c000 0 0 4 &PCI_PIC b>;
+		                 0xc000 0x0 0x0 0x1 &PCI_PIC 8
+		                 0xc000 0x0 0x0 0x2 &PCI_PIC 9
+		                 0xc000 0x0 0x0 0x3 &PCI_PIC 10
+		                 0xc000 0x0 0x0 0x4 &PCI_PIC 11>;
 
 		interrupt-parent = <&PIC>;
-		interrupts = <12 8>;
-		ranges = <42000000 0 80000000 80000000 0 20000000
-		          02000000 0 a0000000 a0000000 0 20000000
-		          01000000 0 00000000 f6000000 0 02000000>;
+		interrupts = <18 8>;
+		ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x20000000
+		          0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
+		          0x1000000 0x0 0x0 0xf6000000 0x0 0x2000000>;
 	};
 
 	soc@f0000000 {
@@ -109,27 +111,27 @@
 		#size-cells = <1>;
 		device_type = "soc";
 		compatible = "fsl,mpc8280", "fsl,pq2-soc";
-		ranges = <00000000 f0000000 00053000>;
+		ranges = <0x0 0xf0000000 0x53000>;
 
 		// Temporary -- will go away once kernel uses ranges for get_immrbase().
-		reg = <f0000000 00053000>;
+		reg = <0xf0000000 0x53000>;
 
 		cpm@119c0 {
 			#address-cells = <1>;
 			#size-cells = <1>;
 			#interrupt-cells = <2>;
 			compatible = "fsl,mpc8280-cpm", "fsl,cpm2";
-			reg = <119c0 30>;
+			reg = <0x119c0 0x30>;
 			ranges;
 
 			muram@0 {
 				#address-cells = <1>;
 				#size-cells = <1>;
-				ranges = <0 0 10000>;
+				ranges = <0x0 0x0 0x10000>;
 
 				data@0 {
 					compatible = "fsl,cpm-muram-data";
-					reg = <0 2000 9800 800>;
+					reg = <0x0 0x2000 0x9800 0x800>;
 				};
 			};
 
@@ -137,53 +139,53 @@
 				compatible = "fsl,mpc8280-brg",
 				             "fsl,cpm2-brg",
 				             "fsl,cpm-brg";
-				reg = <119f0 10 115f0 10>;
+				reg = <0x119f0 0x10 0x115f0 0x10>;
 			};
 
 			serial@11a00 {
 				device_type = "serial";
 				compatible = "fsl,mpc8280-scc-uart",
 				             "fsl,cpm2-scc-uart";
-				reg = <11a00 20 8000 100>;
-				interrupts = <28 8>;
+				reg = <0x11a00 0x20 0x8000 0x100>;
+				interrupts = <40 8>;
 				interrupt-parent = <&PIC>;
 				fsl,cpm-brg = <1>;
-				fsl,cpm-command = <00800000>;
+				fsl,cpm-command = <0x800000>;
 			};
 
 			serial@11a20 {
 				device_type = "serial";
 				compatible = "fsl,mpc8280-scc-uart",
 				             "fsl,cpm2-scc-uart";
-				reg = <11a20 20 8100 100>;
-				interrupts = <29 8>;
+				reg = <0x11a20 0x20 0x8100 0x100>;
+				interrupts = <41 8>;
 				interrupt-parent = <&PIC>;
 				fsl,cpm-brg = <2>;
-				fsl,cpm-command = <04a00000>;
+				fsl,cpm-command = <0x4a00000>;
 			};
 
 			ethernet@11320 {
 				device_type = "network";
 				compatible = "fsl,mpc8280-fcc-enet",
 				             "fsl,cpm2-fcc-enet";
-				reg = <11320 20 8500 100 113b0 1>;
-				interrupts = <21 8>;
+				reg = <0x11320 0x20 0x8500 0x100 0x113b0 0x1>;
+				interrupts = <33 8>;
 				interrupt-parent = <&PIC>;
 				phy-handle = <&PHY0>;
 				linux,network-index = <0>;
-				fsl,cpm-command = <16200300>;
+				fsl,cpm-command = <0x16200300>;
 			};
 
 			ethernet@11340 {
 				device_type = "network";
 				compatible = "fsl,mpc8280-fcc-enet",
 				             "fsl,cpm2-fcc-enet";
-				reg = <11340 20 8600 100 113d0 1>;
-				interrupts = <22 8>;
+				reg = <0x11340 0x20 0x8600 0x100 0x113d0 0x1>;
+				interrupts = <34 8>;
 				interrupt-parent = <&PIC>;
 				phy-handle = <&PHY1>;
 				linux,network-index = <1>;
-				fsl,cpm-command = <1a400300>;
+				fsl,cpm-command = <0x1a400300>;
 				local-mac-address = [00 e0 0c 00 79 01];
 			};
 
@@ -194,21 +196,21 @@
 				             "fsl,cpm2-mdio-bitbang";
 				#address-cells = <1>;
 				#size-cells = <0>;
-				reg = <10d40 14>;
+				reg = <0x10d40 0x14>;
 				fsl,mdio-pin = <9>;
-				fsl,mdc-pin = <a>;
+				fsl,mdc-pin = <10>;
 
 				PHY0: ethernet-phy@0 {
 					interrupt-parent = <&PIC>;
-					interrupts = <19 2>;
-					reg = <0>;
+					interrupts = <25 2>;
+					reg = <0x0>;
 					device_type = "ethernet-phy";
 				};
 
 				PHY1: ethernet-phy@1 {
 					interrupt-parent = <&PIC>;
-					interrupts = <19 2>;
-					reg = <3>;
+					interrupts = <25 2>;
+					reg = <0x3>;
 					device_type = "ethernet-phy";
 				};
 			};
@@ -218,17 +220,17 @@
 				#size-cells = <0>;
 				compatible = "fsl,mpc8280-usb",
 				             "fsl,cpm2-usb";
-				reg = <11b60 18 8b00 100>;
+				reg = <0x11b60 0x18 0x8b00 0x100>;
 				interrupt-parent = <&PIC>;
-				interrupts = <b 8>;
-				fsl,cpm-command = <2e600000>;
+				interrupts = <11 8>;
+				fsl,cpm-command = <0x2e600000>;
 			};
 		};
 
 		PIC: interrupt-controller@10c00 {
 			#interrupt-cells = <2>;
 			interrupt-controller;
-			reg = <10c00 80>;
+			reg = <0x10c00 0x80>;
 			compatible = "fsl,mpc8280-pic", "fsl,cpm2-pic";
 		};
 

arch/powerpc/boot/dts/prpmc2800.dts

@@ -11,6 +11,8 @@
  * if it can determine the exact PrPMC type.
  */
 
+/dts-v1/;
+
 / {
 	#address-cells = <1>;
 	#size-cells = <1>;
@@ -25,46 +27,46 @@
 		PowerPC,7447 {
 			device_type = "cpu";
 			reg = <0>;
-			clock-frequency = <2bb0b140>;	/* Default (733 MHz) */
-			bus-frequency = <7f28155>;	/* 133.333333 MHz */
-			timebase-frequency = <1fca055>;	/* 33.333333 MHz */
-			i-cache-line-size = <20>;
-			d-cache-line-size = <20>;
-			i-cache-size = <8000>;
-			d-cache-size = <8000>;
+			clock-frequency = <733333333>;	/* Default */
+			bus-frequency = <133333333>;
+			timebase-frequency = <33333333>;
+			i-cache-line-size = <32>;
+			d-cache-line-size = <32>;
+			i-cache-size = <32768>;
+			d-cache-size = <32768>;
 		};
 	};
 
 	memory {
 		device_type = "memory";
-		reg = <00000000 20000000>;	/* Default (512MB) */
+		reg = <0x0 0x20000000>;			/* Default (512MB) */
 	};
 
-	mv64x60@f1000000 { /* Marvell Discovery */
+	system-controller@f1000000 { /* Marvell Discovery mv64360 */
 		#address-cells = <1>;
 		#size-cells = <1>;
 		model = "mv64360";			/* Default */
-		compatible = "marvell,mv64x60";
-		clock-frequency = <7f28155>;		/* 133.333333 MHz */
-		reg = <f1000000 00010000>;
-		virtual-reg = <f1000000>;
-		ranges = <88000000 88000000 01000000	/* PCI 0 I/O Space */
-			  80000000 80000000 08000000	/* PCI 0 MEM Space */
-			  a0000000 a0000000 04000000	/* User FLASH */
-			  00000000 f1000000 00010000	/* Bridge's regs */
-			  f2000000 f2000000 00040000>;	/* Integrated SRAM */
+		compatible = "marvell,mv64360";
+		clock-frequency = <133333333>;
+		reg = <0xf1000000 0x10000>;
+		virtual-reg = <0xf1000000>;
+		ranges = <0x88000000 0x88000000 0x1000000 /* PCI 0 I/O Space */
+			  0x80000000 0x80000000 0x8000000 /* PCI 0 MEM Space */
+			  0xa0000000 0xa0000000 0x4000000 /* User FLASH */
+			  0x00000000 0xf1000000 0x0010000 /* Bridge's regs */
+			  0xf2000000 0xf2000000 0x0040000>;/* Integrated SRAM */
 
 		flash@a0000000 {
 			device_type = "rom";
 			compatible = "direct-mapped";
-			reg = <a0000000 4000000>; /* Default (64MB) */
+			reg = <0xa0000000 0x4000000>; /* Default (64MB) */
 			probe-type = "CFI";
 			bank-width = <4>;
-			partitions = <00000000 00100000 /* RO */
-				      00100000 00040001 /* RW */
-				      00140000 00400000 /* RO */
-				      00540000 039c0000 /* RO */
-				      03f00000 00100000>; /* RO */
+			partitions = <0x00000000 0x00100000 /* RO */
+				      0x00100000 0x00040001 /* RW */
+				      0x00140000 0x00400000 /* RO */
+				      0x00540000 0x039c0000 /* RO */
+				      0x03f00000 0x00100000>; /* RO */
 			partition-names = "FW Image A", "FW Config Data", "Kernel Image", "Filesystem", "FW Image B";
 		};
 
@@ -72,171 +74,153 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			device_type = "mdio";
-			compatible = "marvell,mv64x60-mdio";
-			ethernet-phy@1 {
+			compatible = "marvell,mv64360-mdio";
+			PHY0: ethernet-phy@1 {
 				device_type = "ethernet-phy";
 				compatible = "broadcom,bcm5421";
-				interrupts = <4c>;	/* GPP 12 */
-				interrupt-parent = <&/mv64x60/pic>;
+				interrupts = <76>;	/* GPP 12 */
+				interrupt-parent = <&PIC>;
 				reg = <1>;
 			};
-			ethernet-phy@3 {
+			PHY1: ethernet-phy@3 {
 				device_type = "ethernet-phy";
 				compatible = "broadcom,bcm5421";
-				interrupts = <4c>;	/* GPP 12 */
-				interrupt-parent = <&/mv64x60/pic>;
+				interrupts = <76>;	/* GPP 12 */
+				interrupt-parent = <&PIC>;
 				reg = <3>;
 			};
 		};
 
-		ethernet@2000 {
-			reg = <2000 2000>;
-			eth0 {
+		ethernet-group@2000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "marvell,mv64360-eth-group";
+			reg = <0x2000 0x2000>;
+			ethernet@0 {
 				device_type = "network";
-				compatible = "marvell,mv64x60-eth";
-				block-index = <0>;
-				interrupts = <20>;
-				interrupt-parent = <&/mv64x60/pic>;
-				phy = <&/mv64x60/mdio/ethernet-phy@1>;
+				compatible = "marvell,mv64360-eth";
+				reg = <0>;
+				interrupts = <32>;
+				interrupt-parent = <&PIC>;
+				phy = <&PHY0>;
 				local-mac-address = [ 00 00 00 00 00 00 ];
 			};
-			eth1 {
+			ethernet@1 {
 				device_type = "network";
-				compatible = "marvell,mv64x60-eth";
-				block-index = <1>;
-				interrupts = <21>;
-				interrupt-parent = <&/mv64x60/pic>;
-				phy = <&/mv64x60/mdio/ethernet-phy@3>;
+				compatible = "marvell,mv64360-eth";
+				reg = <1>;
+				interrupts = <33>;
+				interrupt-parent = <&PIC>;
+				phy = <&PHY1>;
 				local-mac-address = [ 00 00 00 00 00 00 ];
 			};
 		};
 
-		sdma@4000 {
-			device_type = "dma";
-			compatible = "marvell,mv64x60-sdma";
-			reg = <4000 c18>;
-			virtual-reg = <f1004000>;
-			interrupt-base = <0>;
-			interrupts = <24>;
-			interrupt-parent = <&/mv64x60/pic>;
+		SDMA0: sdma@4000 {
+			compatible = "marvell,mv64360-sdma";
+			reg = <0x4000 0xc18>;
+			virtual-reg = <0xf1004000>;
+			interrupts = <36>;
+			interrupt-parent = <&PIC>;
 		};
 
-		sdma@6000 {
-			device_type = "dma";
-			compatible = "marvell,mv64x60-sdma";
-			reg = <6000 c18>;
-			virtual-reg = <f1006000>;
-			interrupt-base = <0>;
-			interrupts = <26>;
-			interrupt-parent = <&/mv64x60/pic>;
+		SDMA1: sdma@6000 {
+			compatible = "marvell,mv64360-sdma";
+			reg = <0x6000 0xc18>;
+			virtual-reg = <0xf1006000>;
+			interrupts = <38>;
+			interrupt-parent = <&PIC>;
 		};
 
-		brg@b200 {
-			compatible = "marvell,mv64x60-brg";
-			reg = <b200 8>;
+		BRG0: brg@b200 {
+			compatible = "marvell,mv64360-brg";
+			reg = <0xb200 0x8>;
 			clock-src = <8>;
-			clock-frequency = <7ed6b40>;
-			current-speed = <2580>;
-			bcr = <0>;
+			clock-frequency = <133333333>;
+			current-speed = <9600>;
 		};
 
-		brg@b208 {
-			compatible = "marvell,mv64x60-brg";
-			reg = <b208 8>;
+		BRG1: brg@b208 {
+			compatible = "marvell,mv64360-brg";
+			reg = <0xb208 0x8>;
 			clock-src = <8>;
-			clock-frequency = <7ed6b40>;
-			current-speed = <2580>;
-			bcr = <0>;
+			clock-frequency = <133333333>;
+			current-speed = <9600>;
 		};
 
-		cunit@f200 {
-			reg = <f200 200>;
+		CUNIT: cunit@f200 {
+			reg = <0xf200 0x200>;
 		};
 
-		mpscrouting@b400 {
-			reg = <b400 c>;
+		MPSCROUTING: mpscrouting@b400 {
+			reg = <0xb400 0xc>;
 		};
 
-		mpscintr@b800 {
-			reg = <b800 100>;
-			virtual-reg = <f100b800>;
+		MPSCINTR: mpscintr@b800 {
+			reg = <0xb800 0x100>;
+			virtual-reg = <0xf100b800>;
 		};
 
-		mpsc@8000 {
+		MPSC0: mpsc@8000 {
 			device_type = "serial";
-			compatible = "marvell,mpsc";
-			reg = <8000 38>;
-			virtual-reg = <f1008000>;
-			sdma = <&/mv64x60/sdma@4000>;
-			brg = <&/mv64x60/brg@b200>;
-			cunit = <&/mv64x60/cunit@f200>;
-			mpscrouting = <&/mv64x60/mpscrouting@b400>;
-			mpscintr = <&/mv64x60/mpscintr@b800>;
-			block-index = <0>;
-			max_idle = <28>;
-			chr_1 = <0>;
-			chr_2 = <0>;
-			chr_10 = <3>;
-			mpcr = <0>;
-			interrupts = <28>;
-			interrupt-parent = <&/mv64x60/pic>;
+			compatible = "marvell,mv64360-mpsc";
+			reg = <0x8000 0x38>;
+			virtual-reg = <0xf1008000>;
+			sdma = <&SDMA0>;
+			brg = <&BRG0>;
+			cunit = <&CUNIT>;
+			mpscrouting = <&MPSCROUTING>;
+			mpscintr = <&MPSCINTR>;
+			cell-index = <0>;
+			interrupts = <40>;
+			interrupt-parent = <&PIC>;
 		};
 
-		mpsc@9000 {
+		MPSC1: mpsc@9000 {
 			device_type = "serial";
-			compatible = "marvell,mpsc";
-			reg = <9000 38>;
-			virtual-reg = <f1009000>;
-			sdma = <&/mv64x60/sdma@6000>;
-			brg = <&/mv64x60/brg@b208>;
-			cunit = <&/mv64x60/cunit@f200>;
-			mpscrouting = <&/mv64x60/mpscrouting@b400>;
-			mpscintr = <&/mv64x60/mpscintr@b800>;
-			block-index = <1>;
-			max_idle = <28>;
-			chr_1 = <0>;
-			chr_2 = <0>;
-			chr_10 = <3>;
-			mpcr = <0>;
-			interrupts = <2a>;
-			interrupt-parent = <&/mv64x60/pic>;
+			compatible = "marvell,mv64360-mpsc";
+			reg = <0x9000 0x38>;
+			virtual-reg = <0xf1009000>;
+			sdma = <&SDMA1>;
+			brg = <&BRG1>;
+			cunit = <&CUNIT>;
+			mpscrouting = <&MPSCROUTING>;
+			mpscintr = <&MPSCINTR>;
+			cell-index = <1>;
+			interrupts = <42>;
+			interrupt-parent = <&PIC>;
 		};
 
 		wdt@b410 {			/* watchdog timer */
-			compatible = "marvell,mv64x60-wdt";
-			reg = <b410 8>;
-			timeout = <a>;		/* wdt timeout in seconds */
+			compatible = "marvell,mv64360-wdt";
+			reg = <0xb410 0x8>;
 		};
 
 		i2c@c000 {
 			device_type = "i2c";
-			compatible = "marvell,mv64x60-i2c";
-			reg = <c000 20>;
-			virtual-reg = <f100c000>;
-			freq_m = <8>;
-			freq_n = <3>;
-			timeout = <3e8>;		/* 1000 = 1 second */
-			retries = <1>;
-			interrupts = <25>;
-			interrupt-parent = <&/mv64x60/pic>;
+			compatible = "marvell,mv64360-i2c";
+			reg = <0xc000 0x20>;
+			virtual-reg = <0xf100c000>;
+			interrupts = <37>;
+			interrupt-parent = <&PIC>;
 		};
 
-		pic {
+		PIC: pic {
 			#interrupt-cells = <1>;
 			#address-cells = <0>;
-			compatible = "marvell,mv64x60-pic";
-			reg = <0000 88>;
+			compatible = "marvell,mv64360-pic";
+			reg = <0x0 0x88>;
 			interrupt-controller;
 		};
 
 		mpp@f000 {
-			compatible = "marvell,mv64x60-mpp";
-			reg = <f000 10>;
+			compatible = "marvell,mv64360-mpp";
+			reg = <0xf000 0x10>;
 		};
 
 		gpp@f100 {
-			compatible = "marvell,mv64x60-gpp";
-			reg = <f100 20>;
+			compatible = "marvell,mv64360-gpp";
+			reg = <0xf100 0x20>;
 		};
 
 		pci@80000000 {
@@ -244,73 +228,75 @@
 			#size-cells = <2>;
 			#interrupt-cells = <1>;
 			device_type = "pci";
-			compatible = "marvell,mv64x60-pci";
-			reg = <0cf8 8>;
-			ranges = <01000000 0        0 88000000 0 01000000
-				  02000000 0 80000000 80000000 0 08000000>;
-			bus-range = <0 ff>;
-			clock-frequency = <3EF1480>;
-			interrupt-pci-iack = <0c34>;
-			interrupt-parent = <&/mv64x60/pic>;
-			interrupt-map-mask = <f800 0 0 7>;
+			compatible = "marvell,mv64360-pci";
+			reg = <0xcf8 0x8>;
+			ranges = <0x01000000 0x0        0x0
+					0x88000000 0x0 0x01000000
+				  0x02000000 0x0 0x80000000
+				  	0x80000000 0x0 0x08000000>;
+			bus-range = <0 255>;
+			clock-frequency = <66000000>;
+			interrupt-pci-iack = <0xc34>;
+			interrupt-parent = <&PIC>;
+			interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 			interrupt-map = <
 				/* IDSEL 0x0a */
-				5000 0 0 1 &/mv64x60/pic 50
-				5000 0 0 2 &/mv64x60/pic 51
-				5000 0 0 3 &/mv64x60/pic 5b
-				5000 0 0 4 &/mv64x60/pic 5d
+				0x5000 0 0 1 &PIC 80
+				0x5000 0 0 2 &PIC 81
+				0x5000 0 0 3 &PIC 91
+				0x5000 0 0 4 &PIC 93
 
 				/* IDSEL 0x0b */
-				5800 0 0 1 &/mv64x60/pic 5b
-				5800 0 0 2 &/mv64x60/pic 5d
-				5800 0 0 3 &/mv64x60/pic 50
-				5800 0 0 4 &/mv64x60/pic 51
+				0x5800 0 0 1 &PIC 91
+				0x5800 0 0 2 &PIC 93
+				0x5800 0 0 3 &PIC 80
+				0x5800 0 0 4 &PIC 81
 
 				/* IDSEL 0x0c */
-				6000 0 0 1 &/mv64x60/pic 5b
-				6000 0 0 2 &/mv64x60/pic 5d
-				6000 0 0 3 &/mv64x60/pic 50
-				6000 0 0 4 &/mv64x60/pic 51
+				0x6000 0 0 1 &PIC 91
+				0x6000 0 0 2 &PIC 93
+				0x6000 0 0 3 &PIC 80
+				0x6000 0 0 4 &PIC 81
 
 				/* IDSEL 0x0d */
-				6800 0 0 1 &/mv64x60/pic 5d
-				6800 0 0 2 &/mv64x60/pic 50
-				6800 0 0 3 &/mv64x60/pic 51
-				6800 0 0 4 &/mv64x60/pic 5b
+				0x6800 0 0 1 &PIC 93
+				0x6800 0 0 2 &PIC 80
+				0x6800 0 0 3 &PIC 81
+				0x6800 0 0 4 &PIC 91
 			>;
 		};
 
 		cpu-error@0070 {
-			compatible = "marvell,mv64x60-cpu-error";
-			reg = <0070 10 0128 28>;
-			interrupts = <03>;
-			interrupt-parent = <&/mv64x60/pic>;
+			compatible = "marvell,mv64360-cpu-error";
+			reg = <0x70 0x10 0x128 0x28>;
+			interrupts = <3>;
+			interrupt-parent = <&PIC>;
 		};
 
 		sram-ctrl@0380 {
-			compatible = "marvell,mv64x60-sram-ctrl";
-			reg = <0380 80>;
-			interrupts = <0d>;
-			interrupt-parent = <&/mv64x60/pic>;
+			compatible = "marvell,mv64360-sram-ctrl";
+			reg = <0x380 0x80>;
+			interrupts = <13>;
+			interrupt-parent = <&PIC>;
 		};
 
 		pci-error@1d40 {
-			compatible = "marvell,mv64x60-pci-error";
-			reg = <1d40 40 0c28 4>;
-			interrupts = <0c>;
-			interrupt-parent = <&/mv64x60/pic>;
+			compatible = "marvell,mv64360-pci-error";
+			reg = <0x1d40 0x40 0xc28 0x4>;
+			interrupts = <12>;
+			interrupt-parent = <&PIC>;
 		};
 
 		mem-ctrl@1400 {
-			compatible = "marvell,mv64x60-mem-ctrl";
-			reg = <1400 60>;
-			interrupts = <11>;
-			interrupt-parent = <&/mv64x60/pic>;
+			compatible = "marvell,mv64360-mem-ctrl";
+			reg = <0x1400 0x60>;
+			interrupts = <17>;
+			interrupt-parent = <&PIC>;
 		};
 	};
 
 	chosen {
 		bootargs = "ip=on";
-		linux,stdout-path = "/mv64x60@f1000000/mpsc@8000";
+		linux,stdout-path = &MPSC0;
 	};
 };

arch/powerpc/boot/dts/rainier.dts

@@ -254,7 +254,6 @@
 			};
 
 			EMAC0: ethernet@ef600e00 {
-				linux,network-index = <0>;
 				device_type = "network";
 				compatible = "ibm,emac-440grx", "ibm,emac-440epx", "ibm,emac4";
 				interrupt-parent = <&EMAC0>;
@@ -270,7 +269,7 @@
 				mal-tx-channel = <0>;
 				mal-rx-channel = <0>;
 				cell-index = <0>;
-				max-frame-size = <5dc>;
+				max-frame-size = <2328>;
 				rx-fifo-size = <1000>;
 				tx-fifo-size = <800>;
 				phy-mode = "rgmii";
@@ -284,7 +283,6 @@
 			};
 
 			EMAC1: ethernet@ef600f00 {
-				linux,network-index = <1>;
 				device_type = "network";
 				compatible = "ibm,emac-440grx", "ibm,emac-440epx", "ibm,emac4";
 				interrupt-parent = <&EMAC1>;
@@ -300,7 +298,7 @@
 				mal-tx-channel = <1>;
 				mal-rx-channel = <1>;
 				cell-index = <1>;
-				max-frame-size = <5dc>;
+				max-frame-size = <2328>;
 				rx-fifo-size = <1000>;
 				tx-fifo-size = <800>;
 				phy-mode = "rgmii";

arch/powerpc/boot/dts/sbc8641d.dts

@@ -0,0 +1,352 @@
+/*
+ * SBC8641D Device Tree Source
+ *
+ * Copyright 2008 Wind River Systems Inc.
+ *
+ * Paul Gortmaker (see MAINTAINERS for contact information)
+ *
+ * Based largely on the mpc8641_hpcn.dts by Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+	model = "SBC8641D";
+	compatible = "wind,sbc8641";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	aliases {
+		ethernet0 = &enet0;
+		ethernet1 = &enet1;
+		ethernet2 = &enet2;
+		ethernet3 = &enet3;
+		serial0 = &serial0;
+		serial1 = &serial1;
+		pci0 = &pci0;
+		pci1 = &pci1;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		PowerPC,8641@0 {
+			device_type = "cpu";
+			reg = <0>;
+			d-cache-line-size = <32>;
+			i-cache-line-size = <32>;
+			d-cache-size = <32768>;		// L1
+			i-cache-size = <32768>;		// L1
+			timebase-frequency = <0>;	// From uboot
+			bus-frequency = <0>;		// From uboot
+			clock-frequency = <0>;		// From uboot
+		};
+		PowerPC,8641@1 {
+			device_type = "cpu";
+			reg = <1>;
+			d-cache-line-size = <32>;
+			i-cache-line-size = <32>;
+			d-cache-size = <32768>;
+			i-cache-size = <32768>;
+			timebase-frequency = <0>;	// From uboot
+			bus-frequency = <0>;		// From uboot
+			clock-frequency = <0>;		// From uboot
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x20000000>;	// 512M at 0x0
+	};
+
+	localbus@f8005000 {
+		#address-cells = <2>;
+		#size-cells = <1>;
+		compatible = "fsl,mpc8641-localbus", "simple-bus";
+		reg = <0xf8005000 0x1000>;
+		interrupts = <19 2>;
+		interrupt-parent = <&mpic>;
+
+		ranges = <0 0 0xff000000 0x01000000	// 16MB Boot flash
+			  1 0 0xf0000000 0x00010000	// 64KB EEPROM
+			  2 0 0xf1000000 0x00100000	// EPLD (1MB)
+			  3 0 0xe0000000 0x04000000	// 64MB LB SDRAM (CS3)
+			  4 0 0xe4000000 0x04000000	// 64MB LB SDRAM (CS4)
+			  6 0 0xf4000000 0x00100000	// LCD display (1MB)
+			  7 0 0xe8000000 0x04000000>;	// 64MB OneNAND
+
+		flash@0,0 {
+			compatible = "cfi-flash";
+			reg = <0 0 0x01000000>;
+			bank-width = <2>;
+			device-width = <2>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			partition@0 {
+				label = "dtb";
+				reg = <0x00000000 0x00100000>;
+				read-only;
+			};
+			partition@300000 {
+				label = "kernel";
+				reg = <0x00100000 0x00400000>;
+				read-only;
+			};
+			partition@400000 {
+				label = "fs";
+				reg = <0x00500000 0x00a00000>;
+			};
+			partition@700000 {
+				label = "firmware";
+				reg = <0x00f00000 0x00100000>;
+				read-only;
+			};
+		};
+
+		epld@2,0 {
+			compatible = "wrs,epld-localbus";
+			#address-cells = <2>;
+			#size-cells = <1>;
+			reg = <2 0 0x100000>;
+			ranges = <0 0 5 0 1	// User switches
+				  1 0 5 1 1	// Board ID/Rev
+				  3 0 5 3 1>;	// LEDs
+		};
+	};
+
+	soc@f8000000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		device_type = "soc";
+		compatible = "simple-bus";
+		ranges = <0x00000000 0xf8000000 0x00100000>;
+		reg = <0xf8000000 0x00001000>;	// CCSRBAR
+		bus-frequency = <0>;
+
+		i2c@3000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			cell-index = <0>;
+			compatible = "fsl-i2c";
+			reg = <0x3000 0x100>;
+			interrupts = <43 2>;
+			interrupt-parent = <&mpic>;
+			dfsrr;
+		};
+
+		i2c@3100 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			cell-index = <1>;
+			compatible = "fsl-i2c";
+			reg = <0x3100 0x100>;
+			interrupts = <43 2>;
+			interrupt-parent = <&mpic>;
+			dfsrr;
+		};
+
+		mdio@24520 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "fsl,gianfar-mdio";
+			reg = <0x24520 0x20>;
+
+			phy0: ethernet-phy@1f {
+				interrupt-parent = <&mpic>;
+				interrupts = <10 1>;
+				reg = <0x1f>;
+				device_type = "ethernet-phy";
+			};
+			phy1: ethernet-phy@0 {
+				interrupt-parent = <&mpic>;
+				interrupts = <10 1>;
+				reg = <0>;
+				device_type = "ethernet-phy";
+			};
+			phy2: ethernet-phy@1 {
+				interrupt-parent = <&mpic>;
+				interrupts = <10 1>;
+				reg = <1>;
+				device_type = "ethernet-phy";
+			};
+			phy3: ethernet-phy@2 {
+				interrupt-parent = <&mpic>;
+				interrupts = <10 1>;
+				reg = <2>;
+				device_type = "ethernet-phy";
+			};
+		};
+
+		enet0: ethernet@24000 {
+			cell-index = <0>;
+			device_type = "network";
+			model = "TSEC";
+			compatible = "gianfar";
+			reg = <0x24000 0x1000>;
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			interrupts = <29 2 30  2 34 2>;
+			interrupt-parent = <&mpic>;
+			phy-handle = <&phy0>;
+			phy-connection-type = "rgmii-id";
+		};
+
+		enet1: ethernet@25000 {
+			cell-index = <1>;
+			device_type = "network";
+			model = "TSEC";
+			compatible = "gianfar";
+			reg = <0x25000 0x1000>;
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			interrupts = <35 2 36 2 40 2>;
+			interrupt-parent = <&mpic>;
+			phy-handle = <&phy1>;
+			phy-connection-type = "rgmii-id";
+		};
+
+		enet2: ethernet@26000 {
+			cell-index = <2>;
+			device_type = "network";
+			model = "TSEC";
+			compatible = "gianfar";
+			reg = <0x26000 0x1000>;
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			interrupts = <31 2 32 2 33 2>;
+			interrupt-parent = <&mpic>;
+			phy-handle = <&phy2>;
+			phy-connection-type = "rgmii-id";
+		};
+
+		enet3: ethernet@27000 {
+			cell-index = <3>;
+			device_type = "network";
+			model = "TSEC";
+			compatible = "gianfar";
+			reg = <0x27000 0x1000>;
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			interrupts = <37 2 38 2 39 2>;
+			interrupt-parent = <&mpic>;
+			phy-handle = <&phy3>;
+			phy-connection-type = "rgmii-id";
+		};
+
+		serial0: serial@4500 {
+			cell-index = <0>;
+			device_type = "serial";
+			compatible = "ns16550";
+			reg = <0x4500 0x100>;
+			clock-frequency = <0>;
+			interrupts = <42 2>;
+			interrupt-parent = <&mpic>;
+		};
+
+		serial1: serial@4600 {
+			cell-index = <1>;
+			device_type = "serial";
+			compatible = "ns16550";
+			reg = <0x4600 0x100>;
+			clock-frequency = <0>;
+			interrupts = <28 2>;
+			interrupt-parent = <&mpic>;
+		};
+
+		mpic: pic@40000 {
+			clock-frequency = <0>;
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <2>;
+			reg = <0x40000 0x40000>;
+			compatible = "chrp,open-pic";
+			device_type = "open-pic";
+			big-endian;
+		};
+
+		global-utilities@e0000 {
+			compatible = "fsl,mpc8641-guts";
+			reg = <0xe0000 0x1000>;
+			fsl,has-rstcr;
+		};
+	};
+
+	pci0: pcie@f8008000 {
+		cell-index = <0>;
+		compatible = "fsl,mpc8641-pcie";
+		device_type = "pci";
+		#interrupt-cells = <1>;
+		#size-cells = <2>;
+		#address-cells = <3>;
+		reg = <0xf8008000 0x1000>;
+		bus-range = <0x0 0xff>;
+		ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
+			  0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
+		clock-frequency = <33333333>;
+		interrupt-parent = <&mpic>;
+		interrupts = <24 2>;
+		interrupt-map-mask = <0xff00 0 0 7>;
+		interrupt-map = <
+			/* IDSEL 0x0 */
+			0x0000 0 0 1 &mpic 0 1
+			0x0000 0 0 2 &mpic 1 1
+			0x0000 0 0 3 &mpic 2 1
+			0x0000 0 0 4 &mpic 3 1
+			>;
+
+		pcie@0 {
+			reg = <0 0 0 0 0>;
+			#size-cells = <2>;
+			#address-cells = <3>;
+			device_type = "pci";
+			ranges = <0x02000000 0x0 0x80000000
+				  0x02000000 0x0 0x80000000
+				  0x0 0x20000000
+
+				  0x01000000 0x0 0x00000000
+				  0x01000000 0x0 0x00000000
+				  0x0 0x00100000>;
+		};
+
+	};
+
+	pci1: pcie@f8009000 {
+		cell-index = <1>;
+		compatible = "fsl,mpc8641-pcie";
+		device_type = "pci";
+		#interrupt-cells = <1>;
+		#size-cells = <2>;
+		#address-cells = <3>;
+		reg = <0xf8009000 0x1000>;
+		bus-range = <0 0xff>;
+		ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
+			  0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
+		clock-frequency = <33333333>;
+		interrupt-parent = <&mpic>;
+		interrupts = <25 2>;
+		interrupt-map-mask = <0xf800 0 0 7>;
+		interrupt-map = <
+			/* IDSEL 0x0 */
+			0x0000 0 0 1 &mpic 4 1
+			0x0000 0 0 2 &mpic 5 1
+			0x0000 0 0 3 &mpic 6 1
+			0x0000 0 0 4 &mpic 7 1
+			>;
+
+		pcie@0 {
+			reg = <0 0 0 0 0>;
+			#size-cells = <2>;
+			#address-cells = <3>;
+			device_type = "pci";
+			ranges = <0x02000000 0x0 0xa0000000
+				  0x02000000 0x0 0xa0000000
+				  0x0 0x20000000
+
+				  0x01000000 0x0 0x00000000
+				  0x01000000 0x0 0x00000000
+				  0x0 0x00100000>;
+		};
+	};
+};

arch/powerpc/boot/dts/sequoia.dts

@@ -269,7 +269,6 @@
 			};
 
 			EMAC0: ethernet@ef600e00 {
-				linux,network-index = <0>;
 				device_type = "network";
 				compatible = "ibm,emac-440epx", "ibm,emac4";
 				interrupt-parent = <&EMAC0>;
@@ -285,7 +284,7 @@
 				mal-tx-channel = <0>;
 				mal-rx-channel = <0>;
 				cell-index = <0>;
-				max-frame-size = <5dc>;
+				max-frame-size = <2328>;
 				rx-fifo-size = <1000>;
 				tx-fifo-size = <800>;
 				phy-mode = "rgmii";
@@ -299,7 +298,6 @@
 			};
 
 			EMAC1: ethernet@ef600f00 {
-				linux,network-index = <1>;
 				device_type = "network";
 				compatible = "ibm,emac-440epx", "ibm,emac4";
 				interrupt-parent = <&EMAC1>;
@@ -315,7 +313,7 @@
 				mal-tx-channel = <1>;
 				mal-rx-channel = <1>;
 				cell-index = <1>;
-				max-frame-size = <5dc>;
+				max-frame-size = <2328>;
 				rx-fifo-size = <1000>;
 				tx-fifo-size = <800>;
 				phy-mode = "rgmii";

arch/powerpc/boot/dts/taishan.dts

@@ -104,6 +104,16 @@
 		// FIXME: anything else?
 	};
 
+	L2C0: l2c {
+		compatible = "ibm,l2-cache-440gx", "ibm,l2-cache";
+		dcr-reg = <20 8			/* Internal SRAM DCR's */
+			   30 8>;		/* L2 cache DCR's */
+		cache-line-size = <20>;		/* 32 bytes */
+		cache-size = <40000>;		/* L2, 256K */
+		interrupt-parent = <&UIC2>;
+		interrupts = <17 1>;
+	};
+
 	plb {
 		compatible = "ibm,plb-440gx", "ibm,plb4";
 		#address-cells = <2>;
@@ -232,10 +242,18 @@
 				reg = <40000790 8>;
 			};
 
+			TAH0: emac-tah@40000b50 {
+				compatible = "ibm,tah-440gx", "ibm,tah";
+				reg = <40000b50 30>;
+			};
+
+			TAH1: emac-tah@40000d50 {
+				compatible = "ibm,tah-440gx", "ibm,tah";
+				reg = <40000d50 30>;
+			};
 
 			EMAC0: ethernet@40000800 {
 				unused = <1>;
-				linux,network-index = <2>;
 				device_type = "network";
 				compatible = "ibm,emac-440gx", "ibm,emac4";
 				interrupt-parent = <&UIC1>;
@@ -256,7 +274,6 @@
 			};
 		 	EMAC1: ethernet@40000900 {
 				unused = <1>;
-				linux,network-index = <3>;
 				device_type = "network";
 				compatible = "ibm,emac-440gx", "ibm,emac4";
 				interrupt-parent = <&UIC1>;
@@ -277,7 +294,6 @@
 			};
 
 		 	EMAC2: ethernet@40000c00 {
-				linux,network-index = <0>;
 				device_type = "network";
 				compatible = "ibm,emac-440gx", "ibm,emac4";
 				interrupt-parent = <&UIC2>;
@@ -288,7 +304,7 @@
 				mal-tx-channel = <2>;
 				mal-rx-channel = <2>;
 				cell-index = <2>;
-				max-frame-size = <5dc>;
+				max-frame-size = <2328>;
 				rx-fifo-size = <1000>;
 				tx-fifo-size = <800>;
 				phy-mode = "rgmii";
@@ -297,10 +313,11 @@
 				rgmii-channel = <0>;
  				zmii-device = <&ZMII0>;
 				zmii-channel = <2>;
+				tah-device = <&TAH0>;
+				tah-channel = <0>;
 			};
 
 		 	EMAC3: ethernet@40000e00 {
-				linux,network-index = <1>;
 				device_type = "network";
 				compatible = "ibm,emac-440gx", "ibm,emac4";
 				interrupt-parent = <&UIC2>;
@@ -311,7 +328,7 @@
 				mal-tx-channel = <3>;
 				mal-rx-channel = <3>;
 				cell-index = <3>;
-				max-frame-size = <5dc>;
+				max-frame-size = <2328>;
 				rx-fifo-size = <1000>;
 				tx-fifo-size = <800>;
 				phy-mode = "rgmii";
@@ -320,6 +337,8 @@
 				rgmii-channel = <1>;
  				zmii-device = <&ZMII0>;
 				zmii-channel = <3>;
+				tah-device = <&TAH1>;
+				tah-channel = <0>;
 			};
 
 

arch/powerpc/boot/dts/walnut.dts

@@ -125,7 +125,6 @@
 			};
 
 			EMAC: ethernet@ef600800 {
-				linux,network-index = <0>;
 				device_type = "network";
 				compatible = "ibm,emac-405gp", "ibm,emac";
 				interrupt-parent = <&UIC0>;

arch/powerpc/boot/dts/warp.dts

@@ -204,7 +204,6 @@
 			};
 
 			EMAC0: ethernet@ef600e00 {
-				linux,network-index = <0>;
 				device_type = "network";
 				compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac";
 				interrupt-parent = <&UIC1>;

arch/powerpc/boot/dts/yosemite.dts

@@ -0,0 +1,304 @@
+/*
+ * Device Tree Source for AMCC Yosemite
+ *
+ * Copyright 2008 IBM Corp.
+ * Josh Boyer <jwboyer@linux.vnet.ibm.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without
+ * any warranty of any kind, whether express or implied.
+ */
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <1>;
+	model = "amcc,yosemite";
+	compatible = "amcc,yosemite","amcc,bamboo";
+	dcr-parent = <&/cpus/cpu@0>;
+
+	aliases {
+		ethernet0 = &EMAC0;
+		ethernet1 = &EMAC1;
+		serial0 = &UART0;
+		serial1 = &UART1;
+		serial2 = &UART2;
+		serial3 = &UART3;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			model = "PowerPC,440EP";
+			reg = <0>;
+			clock-frequency = <0>; /* Filled in by zImage */
+			timebase-frequency = <0>; /* Filled in by zImage */
+			i-cache-line-size = <20>;
+			d-cache-line-size = <20>;
+			i-cache-size = <8000>;
+			d-cache-size = <8000>;
+			dcr-controller;
+			dcr-access-method = "native";
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0 0 0>; /* Filled in by zImage */
+	};
+
+	UIC0: interrupt-controller0 {
+		compatible = "ibm,uic-440ep","ibm,uic";
+		interrupt-controller;
+		cell-index = <0>;
+		dcr-reg = <0c0 009>;
+		#address-cells = <0>;
+		#size-cells = <0>;
+		#interrupt-cells = <2>;
+	};
+
+	UIC1: interrupt-controller1 {
+		compatible = "ibm,uic-440ep","ibm,uic";
+		interrupt-controller;
+		cell-index = <1>;
+		dcr-reg = <0d0 009>;
+		#address-cells = <0>;
+		#size-cells = <0>;
+		#interrupt-cells = <2>;
+		interrupts = <1e 4 1f 4>; /* cascade */
+		interrupt-parent = <&UIC0>;
+	};
+
+	SDR0: sdr {
+		compatible = "ibm,sdr-440ep";
+		dcr-reg = <00e 002>;
+	};
+
+	CPR0: cpr {
+		compatible = "ibm,cpr-440ep";
+		dcr-reg = <00c 002>;
+	};
+
+	plb {
+		compatible = "ibm,plb-440ep", "ibm,plb-440gp", "ibm,plb4";
+		#address-cells = <2>;
+		#size-cells = <1>;
+		ranges;
+		clock-frequency = <0>; /* Filled in by zImage */
+
+		SDRAM0: sdram {
+			compatible = "ibm,sdram-440ep", "ibm,sdram-405gp";
+			dcr-reg = <010 2>;
+		};
+
+		DMA0: dma {
+			compatible = "ibm,dma-440ep", "ibm,dma-440gp";
+			dcr-reg = <100 027>;
+		};
+
+		MAL0: mcmal {
+			compatible = "ibm,mcmal-440ep", "ibm,mcmal-440gp", "ibm,mcmal";
+			dcr-reg = <180 62>;
+			num-tx-chans = <4>;
+			num-rx-chans = <2>;
+			interrupt-parent = <&MAL0>;
+			interrupts = <0 1 2 3 4>;
+			#interrupt-cells = <1>;
+			#address-cells = <0>;
+			#size-cells = <0>;
+			interrupt-map = </*TXEOB*/ 0 &UIC0 a 4
+					/*RXEOB*/ 1 &UIC0 b 4
+					/*SERR*/  2 &UIC1 0 4
+					/*TXDE*/  3 &UIC1 1 4
+					/*RXDE*/  4 &UIC1 2 4>;
+		};
+
+		POB0: opb {
+			compatible = "ibm,opb-440ep", "ibm,opb-440gp", "ibm,opb";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			/* Bamboo is oddball in the 44x world and doesn't use the ERPN
+			 * bits.
+			 */
+			ranges = <00000000 0 00000000 80000000
+			          80000000 0 80000000 80000000>;
+			interrupt-parent = <&UIC1>;
+			interrupts = <7 4>;
+			clock-frequency = <0>; /* Filled in by zImage */
+
+			EBC0: ebc {
+				compatible = "ibm,ebc-440ep", "ibm,ebc-440gp", "ibm,ebc";
+				dcr-reg = <012 2>;
+				#address-cells = <2>;
+				#size-cells = <1>;
+				clock-frequency = <0>; /* Filled in by zImage */
+				interrupts = <5 1>;
+				interrupt-parent = <&UIC1>;
+			};
+
+			UART0: serial@ef600300 {
+				device_type = "serial";
+				compatible = "ns16550";
+				reg = <ef600300 8>;
+				virtual-reg = <ef600300>;
+				clock-frequency = <0>; /* Filled in by zImage */
+				current-speed = <1c200>;
+				interrupt-parent = <&UIC0>;
+				interrupts = <0 4>;
+			};
+
+			UART1: serial@ef600400 {
+				device_type = "serial";
+				compatible = "ns16550";
+				reg = <ef600400 8>;
+				virtual-reg = <ef600400>;
+				clock-frequency = <0>;
+				current-speed = <0>;
+				interrupt-parent = <&UIC0>;
+				interrupts = <1 4>;
+			};
+
+			UART2: serial@ef600500 {
+				device_type = "serial";
+				compatible = "ns16550";
+				reg = <ef600500 8>;
+				virtual-reg = <ef600500>;
+				clock-frequency = <0>;
+				current-speed = <0>;
+				interrupt-parent = <&UIC0>;
+				interrupts = <3 4>;
+				status = "disabled";
+			};
+
+			UART3: serial@ef600600 {
+				device_type = "serial";
+				compatible = "ns16550";
+				reg = <ef600600 8>;
+				virtual-reg = <ef600600>;
+				clock-frequency = <0>;
+				current-speed = <0>;
+				interrupt-parent = <&UIC0>;
+				interrupts = <4 4>;
+				status = "disabled";
+			};
+
+			IIC0: i2c@ef600700 {
+				compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic";
+				reg = <ef600700 14>;
+				interrupt-parent = <&UIC0>;
+				interrupts = <2 4>;
+			};
+
+			IIC1: i2c@ef600800 {
+				compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic";
+				reg = <ef600800 14>;
+				interrupt-parent = <&UIC0>;
+				interrupts = <7 4>;
+			};
+
+			spi@ef600900 {
+				compatible = "amcc,spi-440ep";
+				reg = <ef600900 6>;
+				interrupts = <8 4>;
+				interrupt-parent = <&UIC0>;
+			};
+
+			ZMII0: emac-zmii@ef600d00 {
+				compatible = "ibm,zmii-440ep", "ibm,zmii-440gp", "ibm,zmii";
+				reg = <ef600d00 c>;
+			};
+
+			EMAC0: ethernet@ef600e00 {
+				device_type = "network";
+				compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac";
+				interrupt-parent = <&UIC1>;
+				interrupts = <1c 4 1d 4>;
+				reg = <ef600e00 70>;
+				local-mac-address = [000000000000];
+				mal-device = <&MAL0>;
+				mal-tx-channel = <0 1>;
+				mal-rx-channel = <0>;
+				cell-index = <0>;
+				max-frame-size = <5dc>;
+				rx-fifo-size = <1000>;
+				tx-fifo-size = <800>;
+				phy-mode = "rmii";
+				phy-map = <00000000>;
+				zmii-device = <&ZMII0>;
+				zmii-channel = <0>;
+			};
+
+			EMAC1: ethernet@ef600f00 {
+				device_type = "network";
+				compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac";
+				interrupt-parent = <&UIC1>;
+				interrupts = <1e 4 1f 4>;
+				reg = <ef600f00 70>;
+				local-mac-address = [000000000000];
+				mal-device = <&MAL0>;
+				mal-tx-channel = <2 3>;
+				mal-rx-channel = <1>;
+				cell-index = <1>;
+				max-frame-size = <5dc>;
+				rx-fifo-size = <1000>;
+				tx-fifo-size = <800>;
+				phy-mode = "rmii";
+				phy-map = <00000000>;
+				zmii-device = <&ZMII0>;
+				zmii-channel = <1>;
+			};
+
+			usb@ef601000 {
+				compatible = "ohci-be";
+				reg = <ef601000 80>;
+				interrupts = <8 4 9 4>;
+				interrupt-parent = < &UIC1 >;
+			};
+		};
+
+		PCI0: pci@ec000000 {
+			device_type = "pci";
+			#interrupt-cells = <1>;
+			#size-cells = <2>;
+			#address-cells = <3>;
+			compatible = "ibm,plb440ep-pci", "ibm,plb-pci";
+			primary;
+			reg = <0 eec00000 8	/* Config space access */
+			       0 eed00000 4	/* IACK */
+			       0 eed00000 4	/* Special cycle */
+			       0 ef400000 40>;	/* Internal registers */
+
+			/* Outbound ranges, one memory and one IO,
+			 * later cannot be changed. Chip supports a second
+			 * IO range but we don't use it for now
+			 */
+			ranges = <02000000 0 a0000000 0 a0000000 0 20000000
+				  01000000 0 00000000 0 e8000000 0 00010000>;
+
+			/* Inbound 2GB range starting at 0 */
+			dma-ranges = <42000000 0 0 0 0 0 80000000>;
+
+			/* Bamboo has all 4 IRQ pins tied together per slot */
+			interrupt-map-mask = <f800 0 0 0>;
+			interrupt-map = <
+				/* IDSEL 1 */
+				0800 0 0 0 &UIC0 1c 8
+
+				/* IDSEL 2 */
+				1000 0 0 0 &UIC0 1b 8
+
+				/* IDSEL 3 */
+				1800 0 0 0 &UIC0 1a 8
+
+				/* IDSEL 4 */
+				2000 0 0 0 &UIC0 19 8
+			>;
+		};
+	};
+
+	chosen {
+		linux,stdout-path = "/plb/opb/serial@ef600300";
+	};
+};

arch/powerpc/boot/ebony.c

@@ -75,7 +75,8 @@ static void ebony_fixups(void)
 
 	ibm440gp_fixup_clocks(sysclk, 6 * 1843200);
 	ibm4xx_sdram_fixup_memsize();
-	dt_fixup_mac_addresses(ebony_mac0, ebony_mac1);
+	dt_fixup_mac_address_by_alias("ethernet0", ebony_mac0);
+	dt_fixup_mac_address_by_alias("ethernet1", ebony_mac1);
 	ibm4xx_fixup_ebc_ranges("/plb/opb/ebc");
 	ebony_flashsel_fixup();
 }

arch/powerpc/boot/libfdt-wrapper.c

@@ -35,7 +35,7 @@
 #define check_err(err) \
 	({ \
 		if (BAD_ERROR(err) || ((err < 0) && DEBUG)) \
-			printf("%s():%d  %s\n\r", __FUNCTION__, __LINE__, \
+			printf("%s():%d  %s\n\r", __func__, __LINE__, \
 			       fdt_strerror(err)); \
 		if (BAD_ERROR(err)) \
 			exit(); \

arch/powerpc/boot/mpc52xx-psc.c

@@ -51,14 +51,9 @@ static unsigned char psc_getc(void)
 
 int mpc5200_psc_console_init(void *devp, struct serial_console_data *scdp)
 {
-	int n;
-
 	/* Get the base address of the psc registers */
-	n = getprop(devp, "virtual-reg", &psc, sizeof(psc));
-	if (n != sizeof(psc)) {
-		if (!dt_xlate_reg(devp, 0, (void *)&psc, NULL))
-			return -1;
-	}
+	if (dt_get_virtual_reg(devp, &psc, 1) < 1)
+		return -1;
 
 	scdp->open = psc_open;
 	scdp->putc = psc_putc;

arch/powerpc/boot/mpsc.c

@@ -141,7 +141,7 @@ int mpsc_console_init(void *devp, struct serial_console_data *scdp)
 	if (mpscintr_base == NULL)
 		goto err_out;
 
-	n = getprop(devp, "block-index", &v, sizeof(v));
+	n = getprop(devp, "cell-index", &v, sizeof(v));
 	if (n != sizeof(v))
 		goto err_out;
 	reg_set = (int)v;

arch/powerpc/boot/mv64x60.c

@@ -535,7 +535,7 @@ u8 *mv64x60_get_bridge_pbase(void)
 	u32 v[2];
 	void *devp;
 
-	devp = finddevice("/mv64x60");
+	devp = find_node_by_compatible(NULL, "marvell,mv64360");
 	if (devp == NULL)
 		goto err_out;
 	if (getprop(devp, "reg", v, sizeof(v)) != sizeof(v))
@@ -553,7 +553,7 @@ u8 *mv64x60_get_bridge_base(void)
 	u32 v;
 	void *devp;
 
-	devp = finddevice("/mv64x60");
+	devp = find_node_by_compatible(NULL, "marvell,mv64360");
 	if (devp == NULL)
 		goto err_out;
 	if (getprop(devp, "virtual-reg", &v, sizeof(v)) != sizeof(v))

arch/powerpc/boot/mv64x60_i2c.c

@@ -185,7 +185,7 @@ int mv64x60_i2c_open(void)
 	u32 v;
 	void *devp;
 
-	devp = finddevice("/mv64x60/i2c");
+	devp = find_node_by_compatible(NULL, "marvell,mv64360-i2c");
 	if (devp == NULL)
 		goto err_out;
 	if (getprop(devp, "virtual-reg", &v, sizeof(v)) != sizeof(v))

arch/powerpc/boot/ns16550.c

@@ -55,15 +55,9 @@ static u8 ns16550_tstc(void)
 int ns16550_console_init(void *devp, struct serial_console_data *scdp)
 {
 	int n;
-	unsigned long reg_phys;
 
-	n = getprop(devp, "virtual-reg", &reg_base, sizeof(reg_base));
-	if (n != sizeof(reg_base)) {
-		if (!dt_xlate_reg(devp, 0, &reg_phys, NULL))
-			return -1;
-
-		reg_base = (void *)reg_phys;
-	}
+	if (dt_get_virtual_reg(devp, (void **)&reg_base, 1) < 1)
+		return -1;
 
 	n = getprop(devp, "reg-shift", &reg_shift, sizeof(reg_shift));
 	if (n != sizeof(reg_shift))

arch/powerpc/boot/ops.h

@@ -95,6 +95,7 @@ int dt_xlate_reg(void *node, int res, unsigned long *addr, unsigned long *size);
 int dt_xlate_addr(void *node, u32 *buf, int buflen, unsigned long *xlated_addr);
 int dt_is_compatible(void *node, const char *compat);
 void dt_get_reg_format(void *node, u32 *naddr, u32 *nsize);
+int dt_get_virtual_reg(void *node, void **addr, int nres);
 
 static inline void *finddevice(const char *name)
 {

arch/powerpc/boot/prpmc2800.c

@@ -344,20 +344,20 @@ static void prpmc2800_bridge_setup(u32 mem_size)
 			acc_bits);
 
 	/* Get the cpu -> pci i/o & mem mappings from the device tree */
-	devp = finddevice("/mv64x60/pci@80000000");
+	devp = find_node_by_compatible(NULL, "marvell,mv64360-pci");
 	if (devp == NULL)
-		fatal("Error: Missing /mv64x60/pci@80000000"
+		fatal("Error: Missing marvell,mv64360-pci"
 				" device tree node\n\r");
 
 	rc = getprop(devp, "ranges", v, sizeof(v));
 	if (rc != sizeof(v))
-		fatal("Error: Can't find /mv64x60/pci@80000000/ranges"
+		fatal("Error: Can't find marvell,mv64360-pci ranges"
 				" property\n\r");
 
 	/* Get the cpu -> pci i/o & mem mappings from the device tree */
-	devp = finddevice("/mv64x60");
+	devp = find_node_by_compatible(NULL, "marvell,mv64360");
 	if (devp == NULL)
-		fatal("Error: Missing /mv64x60 device tree node\n\r");
+		fatal("Error: Missing marvell,mv64360 device tree node\n\r");
 
 	enables = in_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE));
 	enables |= 0x0007fe00; /* Disable all cpu->pci windows */
@@ -429,9 +429,9 @@ static void prpmc2800_fixups(void)
 	setprop(devp, "model", model, l);
 
 	/* Set /cpus/PowerPC,7447/clock-frequency */
-	devp = finddevice("/cpus/PowerPC,7447");
+	devp = find_node_by_prop_value_str(NULL, "device_type", "cpu");
 	if (devp == NULL)
-		fatal("Error: Missing proper /cpus device tree node\n\r");
+		fatal("Error: Missing proper cpu device tree node\n\r");
 	v[0] = bip->core_speed;
 	setprop(devp, "clock-frequency", &v[0], sizeof(v[0]));
 
@@ -443,16 +443,17 @@ static void prpmc2800_fixups(void)
 	v[1] = bip->mem_size;
 	setprop(devp, "reg", v, sizeof(v));
 
-	/* Update /mv64x60/model, if this is a mv64362 */
+	/* Update model, if this is a mv64362 */
 	if (bip->bridge_type == BRIDGE_TYPE_MV64362) {
-		devp = finddevice("/mv64x60");
+		devp = find_node_by_compatible(NULL, "marvell,mv64360");
 		if (devp == NULL)
-			fatal("Error: Missing /mv64x60 device tree node\n\r");
+			fatal("Error: Missing marvell,mv64360"
+					" device tree node\n\r");
 		setprop(devp, "model", "mv64362", strlen("mv64362") + 1);
 	}
 
 	/* Set User FLASH size */
-	devp = finddevice("/mv64x60/flash@a0000000");
+	devp = find_node_by_compatible(NULL, "direct-mapped");
 	if (devp == NULL)
 		fatal("Error: Missing User FLASH device tree node\n\r");
 	rc = getprop(devp, "reg", v, sizeof(v));

arch/powerpc/boot/ps3-head.S

@@ -27,8 +27,9 @@
 /*
  * __system_reset_overlay - The PS3 first stage entry.
  *
- * The bootwraper build script copies the 0x100 bytes at symbol
- * __system_reset_overlay to offset 0x100 of the rom image.
+ * The bootwraper build script copies the 512 bytes at symbol
+ * __system_reset_overlay to offset 0x100 of the rom image.  This symbol
+ * must occupy 512 or less bytes.
  *
  * The PS3 has a single processor with two threads.
  */
@@ -47,8 +48,6 @@ __system_reset_overlay:
 
 	mfspr	r3, 0x88
 	cntlzw.	r3, r3
-	li	r4, 0
-	li	r5, 0
 	beq	1f
 
 	/* Secondary goes to __secondary_hold in kernel. */
@@ -57,8 +56,14 @@ __system_reset_overlay:
 	mtctr	r4
 	bctr
 
-	/* Primary delays then goes to _zimage_start in wrapper. */
 1:
+	/* Save the value at addr zero for a null pointer write check later. */
+
+	li	r4, 0
+	lwz	r3, 0(r4)
+
+	/* Primary delays then goes to _zimage_start in wrapper. */
+
 	or	31, 31, 31 /* db16cyc */
 	or	31, 31, 31 /* db16cyc */
 
@@ -67,16 +72,18 @@ __system_reset_overlay:
 	mtctr	r4
 	bctr
 
+	. = __system_reset_overlay + 512
+
 /*
  * __system_reset_kernel - Place holder for the kernel reset vector.
  *
- * The bootwrapper build script copies 0x100 bytes from offset 0x100
+ * The bootwrapper build script copies 512 bytes from offset 0x100
  * of the rom image to the symbol __system_reset_kernel.  At runtime
- * the bootwrapper program copies the 0x100 bytes at __system_reset_kernel
- * to ram address 0x100.  This symbol must occupy 0x100 bytes.
+ * the bootwrapper program copies the 512 bytes at __system_reset_kernel
+ * to ram address 0x100.  This symbol must occupy 512 bytes.
  */
 
 	.globl __system_reset_kernel
 __system_reset_kernel:
 
-	. = __system_reset_kernel + 0x100
+	. = __system_reset_kernel + 512

arch/powerpc/boot/ps3.c

@@ -27,10 +27,10 @@
 #include "page.h"
 #include "ops.h"
 
-extern s64 lv1_panic(u64 in_1);
-extern s64 lv1_get_logical_partition_id(u64 *out_1);
-extern s64 lv1_get_logical_ppe_id(u64 *out_1);
-extern s64 lv1_get_repository_node_value(u64 in_1, u64 in_2, u64 in_3,
+extern int lv1_panic(u64 in_1);
+extern int lv1_get_logical_partition_id(u64 *out_1);
+extern int lv1_get_logical_ppe_id(u64 *out_1);
+extern int lv1_get_repository_node_value(u64 in_1, u64 in_2, u64 in_3,
 	u64 in_4, u64 in_5, u64 *out_1, u64 *out_2);
 
 #ifdef DEBUG
@@ -46,6 +46,7 @@ BSS_STACK(4096);
  * edit the command line passed to vmlinux (by setting /chosen/bootargs).
  * The buffer is put in it's own section so that tools may locate it easier.
  */
+
 static char cmdline[COMMAND_LINE_SIZE]
 	__attribute__((__section__("__builtin_cmdline")));
 
@@ -75,7 +76,7 @@ static void ps3_exit(void)
 
 static int ps3_repository_read_rm_size(u64 *rm_size)
 {
-	s64 result;
+	int result;
 	u64 lpar_id;
 	u64 ppe_id;
 	u64 v2;
@@ -114,16 +115,17 @@ void ps3_copy_vectors(void)
 {
 	extern char __system_reset_kernel[];
 
-	memcpy((void *)0x100, __system_reset_kernel, 0x100);
-	flush_cache((void *)0x100, 0x100);
+	memcpy((void *)0x100, __system_reset_kernel, 512);
+	flush_cache((void *)0x100, 512);
 }
 
-void platform_init(void)
+void platform_init(unsigned long null_check)
 {
 	const u32 heapsize = 0x1000000 - (u32)_end; /* 16MiB */
 	void *chosen;
 	unsigned long ft_addr;
 	u64 rm_size;
+	unsigned long val;
 
 	console_ops.write = ps3_console_write;
 	platform_ops.exit = ps3_exit;
@@ -151,6 +153,11 @@ void platform_init(void)
 
 	printf(" flat tree at 0x%lx\n\r", ft_addr);
 
+	val = *(unsigned long *)0;
+
+	if (val != null_check)
+		printf("null check failed: %lx != %lx\n\r", val, null_check);
+
 	((kernel_entry_t)0)(ft_addr, 0, NULL);
 
 	ps3_exit();

arch/powerpc/boot/serial.c

@@ -119,7 +119,7 @@ int serial_console_init(void)
 
 	if (dt_is_compatible(devp, "ns16550"))
 		rc = ns16550_console_init(devp, &serial_cd);
-	else if (dt_is_compatible(devp, "marvell,mpsc"))
+	else if (dt_is_compatible(devp, "marvell,mv64360-mpsc"))
 		rc = mpsc_console_init(devp, &serial_cd);
 	else if (dt_is_compatible(devp, "fsl,cpm1-scc-uart") ||
 	         dt_is_compatible(devp, "fsl,cpm1-smc-uart") ||

arch/powerpc/boot/simpleboot.c

@@ -0,0 +1,84 @@
+/*
+ * The simple platform -- for booting when firmware doesn't supply a device
+ *                        tree or any platform configuration information.
+ *                        All data is extracted from an embedded device tree
+ *                        blob.
+ *
+ * Authors: Scott Wood <scottwood@freescale.com>
+ *          Grant Likely <grant.likely@secretlab.ca>
+ *
+ * Copyright (c) 2007 Freescale Semiconductor, Inc.
+ * Copyright (c) 2008 Secret Lab Technologies Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include "ops.h"
+#include "types.h"
+#include "io.h"
+#include "stdio.h"
+#include "libfdt/libfdt.h"
+
+BSS_STACK(4*1024);
+
+void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
+		   unsigned long r6, unsigned long r7)
+{
+	const u32 *na, *ns, *reg, *timebase;
+	u64 memsize64;
+	int node, size, i;
+
+	/* Make sure FDT blob is sane */
+	if (fdt_check_header(_dtb_start) != 0)
+		fatal("Invalid device tree blob\n");
+
+	/* Find the #address-cells and #size-cells properties */
+	node = fdt_path_offset(_dtb_start, "/");
+	if (node < 0)
+		fatal("Cannot find root node\n");
+	na = fdt_getprop(_dtb_start, node, "#address-cells", &size);
+	if (!na || (size != 4))
+		fatal("Cannot find #address-cells property");
+	ns = fdt_getprop(_dtb_start, node, "#size-cells", &size);
+	if (!ns || (size != 4))
+		fatal("Cannot find #size-cells property");
+
+	/* Find the memory range */
+	node = fdt_node_offset_by_prop_value(_dtb_start, -1, "device_type",
+					     "memory", sizeof("memory"));
+	if (node < 0)
+		fatal("Cannot find memory node\n");
+	reg = fdt_getprop(_dtb_start, node, "reg", &size);
+	if (size < (*na+*ns) * sizeof(u32))
+		fatal("cannot get memory range\n");
+
+	/* Only interested in memory based at 0 */
+	for (i = 0; i < *na; i++)
+		if (*reg++ != 0)
+			fatal("Memory range is not based at address 0\n");
+
+	/* get the memsize and trucate it to under 4G on 32 bit machines */
+	memsize64 = 0;
+	for (i = 0; i < *ns; i++)
+		memsize64 = (memsize64 << 32) | *reg++;
+	if (sizeof(void *) == 4 && memsize64 >= 0x100000000ULL)
+		memsize64 = 0xffffffff;
+
+	/* finally, setup the timebase */
+	node = fdt_node_offset_by_prop_value(_dtb_start, -1, "device_type",
+					     "cpu", sizeof("cpu"));
+	if (!node)
+		fatal("Cannot find cpu node\n");
+	timebase = fdt_getprop(_dtb_start, node, "timebase-frequency", &size);
+	if (timebase && (size == 4))
+		timebase_period_ns = 1000000000 / *timebase;
+
+	/* Now we have the memory size; initialize the heap */
+	simple_alloc_init(_end, memsize64 - (unsigned long)_end, 32, 64);
+
+	/* prepare the device tree and find the console */
+	fdt_init(_dtb_start);
+	serial_console_init();
+}

arch/powerpc/boot/treeboot-walnut.c

@@ -68,7 +68,7 @@ static void walnut_fixups(void)
 	ibm4xx_quiesce_eth((u32 *)0xef600800, NULL);
 	ibm4xx_fixup_ebc_ranges("/plb/ebc");
 	walnut_flashsel_fixup();
-	dt_fixup_mac_addresses((u8 *) WALNUT_OPENBIOS_MAC_OFF);
+	dt_fixup_mac_address_by_alias("ethernet0", (u8 *) WALNUT_OPENBIOS_MAC_OFF);
 }
 
 void platform_init(void)

arch/powerpc/boot/virtex405-head.S

@@ -0,0 +1,30 @@
+#include "ppc_asm.h"
+
+	.text
+	.global _zimage_start
+_zimage_start:
+
+	/* PPC errata 213: needed by Virtex-4 FX */
+	mfccr0  0
+	oris    0,0,0x50000000@h
+	mtccr0  0
+
+	/*
+	 * Invalidate the data cache if the data cache is turned off.
+	 * - The 405 core does not invalidate the data cache on power-up
+	 *   or reset but does turn off the data cache. We cannot assume
+	 *   that the cache contents are valid.
+	 * - If the data cache is turned on this must have been done by
+	 *   a bootloader and we assume that the cache contents are
+	 *   valid.
+	 */
+	mfdccr	r9
+	cmplwi	r9,0
+	bne	2f
+	lis	r9,0
+	li	r8,256
+	mtctr	r8
+1:	dccci	r0,r9
+	addi	r9,r9,0x20
+	bdnz	1b
+2:	b	_zimage_start_lib

arch/powerpc/boot/wrapper

@@ -174,7 +174,7 @@ cuboot*)
     *-mpc83*)
         platformo=$object/cuboot-83xx.o
         ;;
-    *-tqm8541|*-mpc8560*|*-tqm8560|*-tqm8555)
+    *-tqm8541|*-mpc8560*|*-tqm8560|*-tqm8555|*-ksi8560*)
         platformo=$object/cuboot-85xx-cpm2.o
         ;;
     *-mpc85*|*-tqm8540|*-sbc85*)
@@ -199,6 +199,10 @@ adder875-redboot)
     platformo="$object/fixed-head.o $object/redboot-8xx.o"
     binary=y
     ;;
+simpleboot-virtex405-*)
+    platformo="$object/virtex405-head.o $object/simpleboot.o"
+    binary=y
+    ;;
 esac
 
 vmz="$tmpdir/`basename \"$kernel\"`.$ext"
@@ -226,10 +230,13 @@ if [ -n "$version" ]; then
     uboot_version="-n Linux-$version"
 fi
 
+# physical offset of kernel image
+membase=`${CROSS}objdump -p "$kernel" | grep -m 1 LOAD | awk '{print $7}'`
+
 case "$platform" in
 uboot)
     rm -f "$ofile"
-    mkimage -A ppc -O linux -T kernel -C gzip -a 00000000 -e 00000000 \
+    mkimage -A ppc -O linux -T kernel -C gzip -a $membase -e $membase \
 	$uboot_version -d "$vmz" "$ofile"
     if [ -z "$cacheit" ]; then
 	rm -f "$vmz"
@@ -298,15 +305,16 @@ treeboot*)
     exit 0
     ;;
 ps3)
-    # The ps3's loader supports loading gzipped binary images from flash
-    # rom to addr zero. The loader enters the image at addr 0x100.  A
-    # bootwrapper overlay is use to arrange for the kernel to be loaded
-    # to addr zero and to have a suitable bootwrapper entry at 0x100.
-    # To construct the rom image, 0x100 bytes from offset 0x100 in the
-    # kernel is copied to the bootwrapper symbol __system_reset_kernel.
-    # The 0x100 bytes at the bootwrapper symbol __system_reset_overlay is
-    # then copied to offset 0x100.  At runtime the bootwrapper program
-    # copies the 0x100 bytes at __system_reset_kernel to addr 0x100.
+    # The ps3's loader supports loading a gzipped binary image from flash
+    # rom to ram addr zero. The loader then enters the system reset
+    # vector at addr 0x100.  A bootwrapper overlay is used to arrange for
+    # a binary image of the kernel to be at addr zero, and yet have a
+    # suitable bootwrapper entry at 0x100.  To construct the final rom
+    # image 512 bytes from offset 0x100 is copied to the bootwrapper
+    # place holder at symbol __system_reset_kernel.  The 512 bytes of the
+    # bootwrapper entry code at symbol __system_reset_overlay is then
+    # copied to offset 0x100.  At runtime the bootwrapper program copies
+    # the data at __system_reset_kernel back to addr 0x100.
 
     system_reset_overlay=0x`${CROSS}nm "$ofile" \
         | grep ' __system_reset_overlay$'       \
@@ -317,7 +325,7 @@ ps3)
         | cut -d' ' -f1`
     system_reset_kernel=`printf "%d" $system_reset_kernel`
     overlay_dest="256"
-    overlay_size="256"
+    overlay_size="512"
 
     ${CROSS}objcopy -O binary "$ofile" "$ofile.bin"
 

arch/powerpc/configs/44x/canyonlands_defconfig

@@ -0,0 +1,721 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.25-rc1
+# Thu Feb 21 14:29:28 2008
+#
+# CONFIG_PPC64 is not set
+
+#
+# Processor support
+#
+# CONFIG_6xx is not set
+# CONFIG_PPC_85xx is not set
+# CONFIG_PPC_8xx is not set
+# CONFIG_40x is not set
+CONFIG_44x=y
+# CONFIG_E200 is not set
+CONFIG_PPC_FPU=y
+CONFIG_4xx=y
+CONFIG_BOOKE=y
+CONFIG_PTE_64BIT=y
+CONFIG_PHYS_64BIT=y
+# CONFIG_PPC_MM_SLICES is not set
+CONFIG_NOT_COHERENT_CACHE=y
+CONFIG_PPC32=y
+CONFIG_WORD_SIZE=32
+CONFIG_PPC_MERGE=y
+CONFIG_MMU=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_HARDIRQS=y
+# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
+CONFIG_IRQ_PER_CPU=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_ARCH_HAS_ILOG2_U32=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
+CONFIG_PPC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_GENERIC_NVRAM=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+CONFIG_PPC_OF=y
+CONFIG_OF=y
+CONFIG_PPC_UDBG_16550=y
+# CONFIG_GENERIC_TBSYNC is not set
+CONFIG_AUDIT_ARCH=y
+CONFIG_GENERIC_BUG=y
+# CONFIG_DEFAULT_UIMAGE is not set
+CONFIG_PPC_DCR_NATIVE=y
+# CONFIG_PPC_DCR_MMIO is not set
+CONFIG_PPC_DCR=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+# CONFIG_FAIR_GROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+# CONFIG_LOGBUFFER is not set
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+CONFIG_LBD=y
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_CLASSIC_RCU=y
+# CONFIG_PREEMPT_RCU is not set
+CONFIG_PPC4xx_PCI_EXPRESS=y
+
+#
+# Platform support
+#
+# CONFIG_PPC_MPC512x is not set
+# CONFIG_PPC_MPC5121 is not set
+# CONFIG_PPC_CELL is not set
+# CONFIG_PPC_CELL_NATIVE is not set
+# CONFIG_PQ2ADS is not set
+# CONFIG_BAMBOO is not set
+# CONFIG_EBONY is not set
+# CONFIG_SEQUOIA is not set
+# CONFIG_TAISHAN is not set
+# CONFIG_KATMAI is not set
+# CONFIG_RAINIER is not set
+# CONFIG_WARP is not set
+CONFIG_CANYONLANDS=y
+CONFIG_460EX=y
+# CONFIG_IPIC is not set
+# CONFIG_MPIC is not set
+# CONFIG_MPIC_WEIRD is not set
+# CONFIG_PPC_I8259 is not set
+# CONFIG_PPC_RTAS is not set
+# CONFIG_MMIO_NVRAM is not set
+# CONFIG_PPC_MPC106 is not set
+# CONFIG_PPC_970_NAP is not set
+# CONFIG_PPC_INDIRECT_IO is not set
+# CONFIG_GENERIC_IOMAP is not set
+# CONFIG_CPU_FREQ is not set
+# CONFIG_FSL_ULI1575 is not set
+
+#
+# Kernel options
+#
+# CONFIG_HIGHMEM is not set
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+# CONFIG_SCHED_HRTICK is not set
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_RCU_TRACE=y
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_MATH_EMULATION is not set
+# CONFIG_IOMMU_HELPER is not set
+CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
+CONFIG_ARCH_HAS_WALK_MEMORY=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_RESOURCES_64BIT=y
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_PROC_DEVICETREE=y
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE=""
+CONFIG_SECCOMP=y
+CONFIG_WANT_DEVICE_TREE=y
+CONFIG_ISA_DMA_API=y
+
+#
+# Bus options
+#
+CONFIG_ZONE_DMA=y
+CONFIG_PPC_INDIRECT_PCI=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_SYSCALL=y
+# CONFIG_PCIEPORTBUS is not set
+CONFIG_ARCH_SUPPORTS_MSI=y
+# CONFIG_PCI_MSI is not set
+CONFIG_PCI_LEGACY=y
+# CONFIG_PCI_DEBUG is not set
+# CONFIG_PCCARD is not set
+# CONFIG_HOTPLUG_PCI is not set
+
+#
+# Advanced setup
+#
+# CONFIG_ADVANCED_OPTIONS is not set
+
+#
+# Default settings for advanced configuration options are used
+#
+CONFIG_HIGHMEM_START=0xfe000000
+CONFIG_LOWMEM_SIZE=0x30000000
+CONFIG_KERNEL_START=0xc0000000
+CONFIG_TASK_SIZE=0xc0000000
+CONFIG_CONSISTENT_START=0xff100000
+CONFIG_CONSISTENT_SIZE=0x00200000
+CONFIG_BOOT_LOAD=0x01000000
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=y
+CONFIG_PROC_EVENTS=y
+# CONFIG_MTD is not set
+CONFIG_OF_DEVICE=y
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=35000
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_XILINX_SYSACE is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_IEEE1394 is not set
+# CONFIG_I2O is not set
+# CONFIG_MACINTOSH_DRIVERS is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_ARCNET is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+# CONFIG_MII is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+CONFIG_IBM_NEW_EMAC=y
+CONFIG_IBM_NEW_EMAC_RXB=256
+CONFIG_IBM_NEW_EMAC_TXB=256
+CONFIG_IBM_NEW_EMAC_POLL_WEIGHT=32
+CONFIG_IBM_NEW_EMAC_RX_COPY_THRESHOLD=256
+CONFIG_IBM_NEW_EMAC_RX_SKB_HEADROOM=0
+# CONFIG_IBM_NEW_EMAC_DEBUG is not set
+CONFIG_IBM_NEW_EMAC_ZMII=y
+CONFIG_IBM_NEW_EMAC_RGMII=y
+CONFIG_IBM_NEW_EMAC_TAH=y
+CONFIG_IBM_NEW_EMAC_EMAC4=y
+# CONFIG_NET_PCI is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_TR is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+# CONFIG_INPUT is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_SERIAL_8250_PCI is not set
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_EXTENDED=y
+# CONFIG_SERIAL_8250_MANY_PORTS is not set
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_RSA is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_UARTLITE is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_NVRAM is not set
+# CONFIG_GEN_RTC is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+# CONFIG_I2C is not set
+
+#
+# SPI support
+#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+CONFIG_DAB=y
+
+#
+# Graphics support
+#
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=m
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_INFINIBAND is not set
+# CONFIG_EDAC is not set
+# CONFIG_RTC_CLASS is not set
+
+#
+# Userspace I/O
+#
+# CONFIG_UIO is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4DEV_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_CRAMFS=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_NLS is not set
+# CONFIG_DLM is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
+# CONFIG_DEBUG_STACKOVERFLOW is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_PAGEALLOC is not set
+CONFIG_DEBUGGER=y
+# CONFIG_KGDB is not set
+# CONFIG_XMON is not set
+# CONFIG_VIRQ_DEBUG is not set
+# CONFIG_BDI_SWITCH is not set
+# CONFIG_PPC_EARLY_DEBUG is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_CRYPTO is not set
+# CONFIG_PPC_CLOCK is not set

arch/powerpc/configs/mpc8313_rdb_defconfig → arch/powerpc/configs/83xx/mpc8313_rdb_defconfig

@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
 # Linux kernel version: 2.6.25-rc6
-# Mon Mar 24 08:48:14 2008
+# Fri Apr 11 11:10:09 2008
 #
 # CONFIG_PPC64 is not set
 
@@ -196,6 +196,7 @@ CONFIG_PREEMPT_NONE=y
 # CONFIG_PREEMPT is not set
 CONFIG_BINFMT_ELF=y
 # CONFIG_BINFMT_MISC is not set
+CONFIG_FORCE_MAX_ZONEORDER=11
 # CONFIG_IOMMU_HELPER is not set
 CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
 CONFIG_ARCH_HAS_WALK_MEMORY=y
@@ -360,7 +361,7 @@ CONFIG_MTD=y
 CONFIG_MTD_PARTITIONS=y
 # CONFIG_MTD_REDBOOT_PARTS is not set
 # CONFIG_MTD_CMDLINE_PARTS is not set
-# CONFIG_MTD_OF_PARTS is not set
+CONFIG_MTD_OF_PARTS=y
 
 #
 # User Modules And Translation Layers
@@ -436,7 +437,7 @@ CONFIG_MTD_NAND_IDS=y
 # CONFIG_MTD_NAND_NANDSIM is not set
 # CONFIG_MTD_NAND_PLATFORM is not set
 # CONFIG_MTD_ALAUDA is not set
-# CONFIG_MTD_NAND_FSL_ELBC is not set
+CONFIG_MTD_NAND_FSL_ELBC=y
 # CONFIG_MTD_ONENAND is not set
 
 #
@@ -1293,6 +1294,7 @@ CONFIG_PLIST=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
+CONFIG_HAVE_LMB=y
 
 #
 # Kernel hacking

arch/powerpc/configs/85xx/ksi8560_defconfig

@@ -0,0 +1,899 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.24
+# Mon Feb 11 16:25:19 2008
+#
+# CONFIG_PPC64 is not set
+
+#
+# Processor support
+#
+# CONFIG_6xx is not set
+CONFIG_PPC_85xx=y
+# CONFIG_PPC_8xx is not set
+# CONFIG_40x is not set
+# CONFIG_44x is not set
+# CONFIG_E200 is not set
+CONFIG_E500=y
+CONFIG_BOOKE=y
+CONFIG_FSL_BOOKE=y
+CONFIG_FSL_EMB_PERFMON=y
+# CONFIG_PHYS_64BIT is not set
+CONFIG_SPE=y
+# CONFIG_PPC_MM_SLICES is not set
+CONFIG_PPC32=y
+CONFIG_WORD_SIZE=32
+CONFIG_PPC_MERGE=y
+CONFIG_MMU=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_HARDIRQS=y
+# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
+CONFIG_IRQ_PER_CPU=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_ARCH_HAS_ILOG2_U32=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
+CONFIG_PPC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_GENERIC_NVRAM=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+CONFIG_PPC_OF=y
+CONFIG_OF=y
+CONFIG_PPC_UDBG_16550=y
+# CONFIG_GENERIC_TBSYNC is not set
+CONFIG_AUDIT_ARCH=y
+CONFIG_GENERIC_BUG=y
+CONFIG_DEFAULT_UIMAGE=y
+# CONFIG_PPC_DCR_NATIVE is not set
+# CONFIG_PPC_DCR_MMIO is not set
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_FAIR_USER_SCHED=y
+# CONFIG_FAIR_CGROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+# CONFIG_MODULES is not set
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_CLASSIC_RCU=y
+# CONFIG_PREEMPT_RCU is not set
+
+#
+# Platform support
+#
+# CONFIG_PPC_MPC512x is not set
+# CONFIG_PPC_MPC5121 is not set
+# CONFIG_PPC_CELL is not set
+# CONFIG_PPC_CELL_NATIVE is not set
+# CONFIG_PQ2ADS is not set
+CONFIG_MPC85xx=y
+# CONFIG_MPC8540_ADS is not set
+# CONFIG_MPC8560_ADS is not set
+# CONFIG_MPC85xx_CDS is not set
+# CONFIG_MPC85xx_MDS is not set
+# CONFIG_MPC85xx_DS is not set
+CONFIG_KSI8560=y
+# CONFIG_STX_GP3 is not set
+# CONFIG_TQM8540 is not set
+# CONFIG_TQM8541 is not set
+# CONFIG_TQM8555 is not set
+# CONFIG_TQM8560 is not set
+# CONFIG_SBC8548 is not set
+# CONFIG_SBC8560 is not set
+# CONFIG_IPIC is not set
+CONFIG_MPIC=y
+# CONFIG_MPIC_WEIRD is not set
+# CONFIG_PPC_I8259 is not set
+# CONFIG_PPC_RTAS is not set
+# CONFIG_MMIO_NVRAM is not set
+# CONFIG_PPC_MPC106 is not set
+# CONFIG_PPC_970_NAP is not set
+# CONFIG_PPC_INDIRECT_IO is not set
+# CONFIG_GENERIC_IOMAP is not set
+# CONFIG_CPU_FREQ is not set
+CONFIG_CPM2=y
+CONFIG_PPC_CPM_NEW_BINDING=y
+# CONFIG_FSL_ULI1575 is not set
+CONFIG_CPM=y
+
+#
+# Kernel options
+#
+CONFIG_HIGHMEM=y
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+# CONFIG_SCHED_HRTICK is not set
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_RCU_TRACE=y
+CONFIG_BINFMT_ELF=y
+CONFIG_BINFMT_MISC=y
+CONFIG_MATH_EMULATION=y
+# CONFIG_IOMMU_HELPER is not set
+CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_PROC_DEVICETREE is not set
+# CONFIG_CMDLINE_BOOL is not set
+# CONFIG_PM is not set
+# CONFIG_SECCOMP is not set
+CONFIG_WANT_DEVICE_TREE=y
+CONFIG_ISA_DMA_API=y
+
+#
+# Bus options
+#
+CONFIG_ZONE_DMA=y
+CONFIG_FSL_SOC=y
+# CONFIG_PCI is not set
+# CONFIG_PCI_DOMAINS is not set
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Advanced setup
+#
+# CONFIG_ADVANCED_OPTIONS is not set
+
+#
+# Default settings for advanced configuration options are used
+#
+CONFIG_HIGHMEM_START=0xfe000000
+CONFIG_LOWMEM_SIZE=0x30000000
+CONFIG_KERNEL_START=0xc0000000
+CONFIG_TASK_SIZE=0xc0000000
+CONFIG_BOOT_LOAD=0x00800000
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+CONFIG_MTD_PHYSMAP_OF=y
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+CONFIG_OF_DEVICE=y
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=32768
+CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_IDE=y
+CONFIG_IDE_MAX_HWIFS=4
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_IDE_SATA is not set
+# CONFIG_BLK_DEV_IDEDISK is not set
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_IDE_TASK_IOCTL is not set
+CONFIG_IDE_PROC_FS=y
+
+#
+# IDE chipset support/bugfixes
+#
+CONFIG_IDE_GENERIC=y
+# CONFIG_BLK_DEV_PLATFORM is not set
+# CONFIG_BLK_DEV_IDEDMA is not set
+CONFIG_IDE_ARCH_OBSOLETE_INIT=y
+# CONFIG_BLK_DEV_HD is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_MACINTOSH_DRIVERS is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+CONFIG_MARVELL_PHY=y
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_FIXED_PHY is not set
+CONFIG_MDIO_BITBANG=y
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+CONFIG_FS_ENET=y
+# CONFIG_FS_ENET_HAS_SCC is not set
+CONFIG_FS_ENET_HAS_FCC=y
+CONFIG_FS_ENET_MDIO_FCC=y
+CONFIG_NETDEV_1000=y
+# CONFIG_E1000E_ENABLED is not set
+CONFIG_GIANFAR=y
+CONFIG_GFAR_NAPI=y
+CONFIG_NETDEV_10000=y
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_UARTLITE is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_SERIAL_CPM=y
+CONFIG_SERIAL_CPM_CONSOLE=y
+CONFIG_SERIAL_CPM_SCC1=y
+# CONFIG_SERIAL_CPM_SCC2 is not set
+# CONFIG_SERIAL_CPM_SCC3 is not set
+# CONFIG_SERIAL_CPM_SCC4 is not set
+# CONFIG_SERIAL_CPM_SMC1 is not set
+# CONFIG_SERIAL_CPM_SMC2 is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_NVRAM is not set
+CONFIG_GEN_RTC=y
+# CONFIG_GEN_RTC_X is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+
+#
+# SPI support
+#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+CONFIG_DAB=y
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=y
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+CONFIG_USB_SUPPORT=y
+# CONFIG_USB_ARCH_HAS_HCD is not set
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+# CONFIG_USB_GADGET is not set
+# CONFIG_MMC is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_EDAC is not set
+# CONFIG_RTC_CLASS is not set
+
+#
+# Userspace I/O
+#
+# CONFIG_UIO is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+# CONFIG_NFS_V3 is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+# CONFIG_MSDOS_PARTITION is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+# CONFIG_NLS is not set
+# CONFIG_DLM is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+CONFIG_DEBUG_MUTEXES=y
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_HIGHMEM is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+CONFIG_FORCED_INLINING=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
+# CONFIG_DEBUG_STACKOVERFLOW is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_PAGEALLOC is not set
+# CONFIG_DEBUGGER is not set
+# CONFIG_KGDB_CONSOLE is not set
+# CONFIG_VIRQ_DEBUG is not set
+# CONFIG_BDI_SWITCH is not set
+# CONFIG_PPC_EARLY_DEBUG is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+# CONFIG_CRYPTO_SEQIV is not set
+# CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_WP512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_XTS is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_LZO is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_PPC_CLOCK is not set
+CONFIG_PPC_LIB_RHEAP=y

arch/powerpc/configs/mpc8544_ds_defconfig → arch/powerpc/configs/85xx/mpc8544_ds_defconfig

@@ -162,6 +162,7 @@ CONFIG_MPC85xx=y
 # CONFIG_MPC85xx_CDS is not set
 # CONFIG_MPC85xx_MDS is not set
 CONFIG_MPC85xx_DS=y
+# CONFIG_KSI8560 is not set
 # CONFIG_STX_GP3 is not set
 # CONFIG_TQM8540 is not set
 # CONFIG_TQM8541 is not set
@@ -202,6 +203,7 @@ CONFIG_PREEMPT_NONE=y
 # CONFIG_PREEMPT is not set
 CONFIG_BINFMT_ELF=y
 CONFIG_BINFMT_MISC=m
+CONFIG_FORCE_MAX_ZONEORDER=11
 CONFIG_MATH_EMULATION=y
 # CONFIG_IOMMU_HELPER is not set
 CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
@@ -1255,7 +1257,19 @@ CONFIG_RTC_DRV_CMOS=y
 #
 # on-CPU RTC drivers
 #
-# CONFIG_DMADEVICES is not set
+CONFIG_DMADEVICES=y
+
+#
+# DMA Devices
+#
+CONFIG_FSL_DMA=y
+# CONFIG_FSL_DMA_SELFTEST is not set
+CONFIG_DMA_ENGINE=y
+
+#
+# DMA Clients
+#
+# CONFIG_NET_DMA is not set
 
 #
 # Userspace I/O
@@ -1447,6 +1461,7 @@ CONFIG_PLIST=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
+CONFIG_HAVE_LMB=y
 
 #
 # Kernel hacking