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@@ -90,6 +90,7 @@ enum {
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board_ahci_mv = 4,
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board_ahci_mv = 4,
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board_ahci_sb700 = 5,
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board_ahci_sb700 = 5,
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board_ahci_mcp65 = 6,
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board_ahci_mcp65 = 6,
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+ board_ahci_nopmp = 7,
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/* global controller registers */
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/* global controller registers */
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HOST_CAP = 0x00, /* host capabilities */
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HOST_CAP = 0x00, /* host capabilities */
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@@ -401,6 +402,14 @@ static const struct ata_port_info ahci_port_info[] = {
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.udma_mask = ATA_UDMA6,
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.udma_mask = ATA_UDMA6,
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.port_ops = &ahci_ops,
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.port_ops = &ahci_ops,
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},
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},
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+ /* board_ahci_nopmp */
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+ {
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+ AHCI_HFLAGS (AHCI_HFLAG_NO_PMP),
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+ .flags = AHCI_FLAG_COMMON,
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+ .pio_mask = 0x1f, /* pio0-4 */
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+ .udma_mask = ATA_UDMA6,
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+ .port_ops = &ahci_ops,
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+ },
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};
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};
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static const struct pci_device_id ahci_pci_tbl[] = {
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static const struct pci_device_id ahci_pci_tbl[] = {
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@@ -525,9 +534,9 @@ static const struct pci_device_id ahci_pci_tbl[] = {
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{ PCI_VDEVICE(NVIDIA, 0x0bc7), board_ahci }, /* MCP7B */
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{ PCI_VDEVICE(NVIDIA, 0x0bc7), board_ahci }, /* MCP7B */
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/* SiS */
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/* SiS */
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- { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
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- { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
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- { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
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+ { PCI_VDEVICE(SI, 0x1184), board_ahci_nopmp }, /* SiS 966 */
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+ { PCI_VDEVICE(SI, 0x1185), board_ahci_nopmp }, /* SiS 968 */
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+ { PCI_VDEVICE(SI, 0x0186), board_ahci_nopmp }, /* SiS 968 */
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/* Marvell */
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/* Marvell */
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{ PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
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{ PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
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