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@@ -376,7 +376,7 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
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locktime = ((2000 * prediv) / 100);
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prediv = (prediv - 1) | PLLDIV_EN;
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} else {
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- locktime = 20;
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+ locktime = PLL_LOCK_TIME;
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}
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if (postdiv)
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postdiv = (postdiv - 1) | PLLDIV_EN;
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@@ -389,12 +389,7 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
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ctrl &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN);
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__raw_writel(ctrl, pll->base + PLLCTL);
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- /*
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- * Wait for 4 OSCIN/CLKIN cycles to ensure that the PLLC has switched
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- * to bypass mode. Delay of 1us ensures we are good for all > 4MHz
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- * OSCIN/CLKIN inputs. Typically the input is ~25MHz.
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- */
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- udelay(1);
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+ udelay(PLL_BYPASS_TIME);
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/* Reset and enable PLL */
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ctrl &= ~(PLLCTL_PLLRST | PLLCTL_PLLDIS);
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@@ -408,11 +403,7 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
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if (pll->flags & PLL_HAS_POSTDIV)
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__raw_writel(postdiv, pll->base + POSTDIV);
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- /*
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- * Wait for PLL to reset properly, OMAP-L138 datasheet says
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- * 'min' time = 125ns
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- */
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- udelay(1);
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+ udelay(PLL_RESET_TIME);
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/* Bring PLL out of reset */
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ctrl |= PLLCTL_PLLRST;
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