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@@ -60,14 +60,6 @@
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#define PCIE_DEBUG_CTRL 0x1a60
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#define PCIE_DEBUG_SOFT_RESET BIT(20)
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-/*
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- * This product ID is registered by Marvell, and used when the Marvell
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- * SoC is not the root complex, but an endpoint on the PCIe bus. It is
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- * therefore safe to re-use this PCI ID for our emulated PCI-to-PCI
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- * bridge.
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- */
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-#define MARVELL_EMULATED_PCI_PCI_BRIDGE_ID 0x7846
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-
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/* PCI configuration space of a PCI-to-PCI bridge */
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struct mvebu_sw_pci_bridge {
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u16 vendor;
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@@ -377,7 +369,8 @@ static void mvebu_sw_pci_bridge_init(struct mvebu_pcie_port *port)
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bridge->class = PCI_CLASS_BRIDGE_PCI;
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bridge->vendor = PCI_VENDOR_ID_MARVELL;
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- bridge->device = MARVELL_EMULATED_PCI_PCI_BRIDGE_ID;
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+ bridge->device = mvebu_readl(port, PCIE_DEV_ID_OFF) >> 16;
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+ bridge->revision = mvebu_readl(port, PCIE_DEV_REV_OFF) & 0xff;
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bridge->header_type = PCI_HEADER_TYPE_BRIDGE;
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bridge->cache_line_size = 0x10;
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