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@@ -10673,17 +10673,6 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
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tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
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- /* Back to back register writes can cause problems on this chip,
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- * the workaround is to read back all reg writes except those to
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- * mailbox regs. See tg3_write_indirect_reg32().
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- *
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- * PCI Express 5750_A0 rev chips need this workaround too.
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- */
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- if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
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- ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
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- tp->pci_chip_rev_id == CHIPREV_ID_5750_A0))
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- tp->tg3_flags |= TG3_FLAG_5701_REG_WRITE_BUG;
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-
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if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
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tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
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if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
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@@ -10707,8 +10696,19 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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/* Various workaround register access methods */
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if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
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tp->write32 = tg3_write_indirect_reg32;
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- else if (tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG)
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+ else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
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+ ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
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+ tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
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+ /*
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+ * Back to back register writes can cause problems on these
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+ * chips, the workaround is to read back all reg writes
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+ * except those to mailbox regs.
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+ *
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+ * See tg3_write_indirect_reg32().
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+ */
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tp->write32 = tg3_write_flush_reg32;
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+ }
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+
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if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
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(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
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