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@@ -46,6 +46,22 @@ asmlinkage void resume(void);
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} while (0)
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+/*
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+ * Force strict CPU ordering.
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+ * Not really required on m68k...
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+ */
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+#define nop() do { asm volatile ("nop"); barrier(); } while (0)
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+#define mb() barrier()
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+#define rmb() barrier()
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+#define wmb() barrier()
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+#define read_barrier_depends() ((void)0)
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+#define set_mb(var, value) ({ (var) = (value); wmb(); })
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+
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+#define smp_mb() barrier()
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+#define smp_rmb() barrier()
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+#define smp_wmb() barrier()
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+#define smp_read_barrier_depends() ((void)0)
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+
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/* interrupt control.. */
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#if 0
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#define local_irq_enable() asm volatile ("andiw %0,%%sr": : "i" (ALLOWINT) : "memory")
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@@ -70,23 +86,6 @@ static inline int irqs_disabled(void)
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/* For spinlocks etc */
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#define local_irq_save(x) ({ local_save_flags(x); local_irq_disable(); })
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-/*
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- * Force strict CPU ordering.
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- * Not really required on m68k...
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- */
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-#define nop() do { asm volatile ("nop"); barrier(); } while (0)
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-#define mb() barrier()
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-#define rmb() barrier()
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-#define wmb() barrier()
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-#define read_barrier_depends() ((void)0)
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-#define set_mb(var, value) ({ (var) = (value); wmb(); })
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-
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-#define smp_mb() barrier()
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-#define smp_rmb() barrier()
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-#define smp_wmb() barrier()
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-#define smp_read_barrier_depends() ((void)0)
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-
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-
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#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
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struct __xchg_dummy { unsigned long a[100]; };
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