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@@ -807,7 +807,6 @@ static int zd1211_hw_init_hmac(struct zd_chip *chip)
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{ CR_ACK_TIMEOUT_EXT, 0x80 },
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{ CR_ADDA_PWR_DWN, 0x00 },
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{ CR_ACK_TIME_80211, 0x100 },
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- { CR_IFS_VALUE, 0x547c032 },
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{ CR_RX_PE_DELAY, 0x70 },
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{ CR_PS_CTRL, 0x10000000 },
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{ CR_RTS_CTS_RATE, 0x02030203 },
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@@ -854,7 +853,6 @@ static int zd1211b_hw_init_hmac(struct zd_chip *chip)
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{ CR_ACK_TIMEOUT_EXT, 0x80 },
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{ CR_ADDA_PWR_DWN, 0x00 },
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{ CR_ACK_TIME_80211, 0x100 },
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- { CR_IFS_VALUE, 0x547c032 },
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{ CR_RX_PE_DELAY, 0x70 },
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{ CR_PS_CTRL, 0x10000000 },
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{ CR_RTS_CTS_RATE, 0x02030203 },
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@@ -970,10 +968,15 @@ static int hw_init(struct zd_chip *chip)
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r = hw_init_hmac(chip);
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if (r)
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return r;
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- r = set_beacon_interval(chip, 100);
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+
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+ /* Although the vendor driver defaults to a different value during
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+ * init, it overwrites the IFS value with the following every time
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+ * the channel changes. We should aim to be more intelligent... */
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+ r = zd_iowrite32_locked(chip, IFS_VALUE_DEFAULT, CR_IFS_VALUE);
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if (r)
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return r;
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- return 0;
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+
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+ return set_beacon_interval(chip, 100);
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}
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#ifdef DEBUG
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