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@@ -52,24 +52,46 @@ static void sun4i_clkevt_sync(void)
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cpu_relax();
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}
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+static void sun4i_clkevt_time_stop(u8 timer)
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+{
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+ u32 val = readl(timer_base + TIMER_CTL_REG(timer));
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+ writel(val & ~TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(timer));
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+ sun4i_clkevt_sync();
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+}
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+
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+static void sun4i_clkevt_time_setup(u8 timer, unsigned long delay)
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+{
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+ writel(delay, timer_base + TIMER_INTVAL_REG(timer));
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+}
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+
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+static void sun4i_clkevt_time_start(u8 timer, bool periodic)
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+{
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+ u32 val = readl(timer_base + TIMER_CTL_REG(timer));
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+
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+ if (periodic)
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+ val &= ~TIMER_CTL_ONESHOT;
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+ else
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+ val |= TIMER_CTL_ONESHOT;
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+
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+ writel(val | TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(timer));
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+}
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+
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static void sun4i_clkevt_mode(enum clock_event_mode mode,
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struct clock_event_device *clk)
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{
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- u32 u = readl(timer_base + TIMER_CTL_REG(0));
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-
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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- u &= ~(TIMER_CTL_ONESHOT);
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- writel(u | TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(0));
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+ sun4i_clkevt_time_stop(0);
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+ sun4i_clkevt_time_start(0, true);
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break;
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-
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case CLOCK_EVT_MODE_ONESHOT:
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- writel(u | TIMER_CTL_ONESHOT, timer_base + TIMER_CTL_REG(0));
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+ sun4i_clkevt_time_stop(0);
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+ sun4i_clkevt_time_start(0, false);
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break;
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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default:
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- writel(u & ~(TIMER_CTL_ENABLE), timer_base + TIMER_CTL_REG(0));
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+ sun4i_clkevt_time_stop(0);
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break;
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}
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}
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@@ -77,15 +99,9 @@ static void sun4i_clkevt_mode(enum clock_event_mode mode,
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static int sun4i_clkevt_next_event(unsigned long evt,
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struct clock_event_device *unused)
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{
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- u32 val = readl(timer_base + TIMER_CTL_REG(0));
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- writel(val & ~TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(0));
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- sun4i_clkevt_sync();
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-
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- writel(evt, timer_base + TIMER_INTVAL_REG(0));
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-
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- val = readl(timer_base + TIMER_CTL_REG(0));
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- writel(val | TIMER_CTL_ENABLE | TIMER_CTL_AUTORELOAD,
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- timer_base + TIMER_CTL_REG(0));
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+ sun4i_clkevt_time_stop(0);
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+ sun4i_clkevt_time_setup(0, evt);
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+ sun4i_clkevt_time_start(0, false);
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return 0;
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}
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